[Mesa-dev] [PATCH 1/3] radeonsi: simplify DCC handling in si_initialize_color_surface

[Nicolai Hähnle]

With the remark on patch 2 (radeonsi: properly check if DCC is enabled 
and allocated), the series is

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 24.10.2015 17:49, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
>   src/gallium/drivers/radeonsi/si_state.c | 10 +++-------
>   1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 384c8e2..c87f661 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -1926,8 +1926,9 @@ static void si_initialize_color_surface(struct si_context *sctx,
>   	surf->cb_color_info = color_info;
>   	surf->cb_color_attrib = color_attrib;
>
> -	if (sctx->b.chip_class >= VI) {
> +	if (sctx->b.chip_class >= VI && rtex->surface.dcc_enabled) {
>   		unsigned max_uncompressed_block_size = 2;
> +		uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
>
>   		if (rtex->surface.nsamples > 1) {
>   			if (rtex->surface.bpe == 1)
> @@ -1938,12 +1939,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
>
>   		surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
>   		                       S_028C78_INDEPENDENT_64B_BLOCKS(1);
> -
> -		if (rtex->surface.dcc_enabled) {
> -			uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
> -
> -			surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8;
> -		}
> +		surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8;
>   	}
>
>   	if (rtex->fmask.size) {
>