[Mesa-dev] [Mesa-dev, 3/4] i965/cs: Initialize gl_WorkGroupID variable from payload

[Kristian Høgsberg]

Jordan Justen <jordan.l.justen at intel.com> writes:

> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>

I double checked the GPGPU payload, this looks corrent.

Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>

>
> ---
> src/mesa/drivers/dri/i965/brw_cs.cpp | 19 +++++++++++++++++++
>  src/mesa/drivers/dri/i965/brw_fs.h   |  1 +
>  2 files changed, 20 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_cs.cpp b/src/mesa/drivers/dri/i965/brw_cs.cpp
> index 3e68327..14c69a2 100644
> --- a/src/mesa/drivers/dri/i965/brw_cs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_cs.cpp
> @@ -627,3 +627,22 @@ const struct brw_tracked_state gen7_cs_push_constants = {
>     },
>     /* .emit = */ gen7_upload_cs_push_constants,
>  };
> +
> +
> +fs_reg *
> +fs_visitor::emit_cs_work_group_id_setup()
> +{
> +   assert(stage == MESA_SHADER_COMPUTE);
> +
> +   fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::uvec3_type));
> +
> +   struct brw_reg r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
> +   struct brw_reg r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD));
> +   struct brw_reg r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD));
> +
> +   bld.MOV(*reg, r0_1);
> +   bld.MOV(offset(*reg, bld, 1), r0_6);
> +   bld.MOV(offset(*reg, bld, 2), r0_7);
> +
> +   return reg;
> +}
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
> index 1e1974f..60c4dfa 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.h
> +++ b/src/mesa/drivers/dri/i965/brw_fs.h
> @@ -278,6 +278,7 @@ public:
>     void emit_urb_writes();
>     void emit_cs_terminate();
>     fs_reg *emit_cs_local_invocation_id_setup();
> +   fs_reg *emit_cs_work_group_id_setup();
>  
>     void emit_barrier();
>