[Mesa-dev] [PATCH V2 6/8] i965: Fix {src, dst}_pitch alignment check for XY_SRC_COPY_BLT

[Chad Versace]

On Wed 19 Aug 2015, Anuj Phogat wrote:
> Current code checks the alignment restrictions only for Y tiling.
> From Broadwell PRM vol 10:
> 
>  "pitch is of 512Byte granularity for Tile-X: This means the tiled-x
>   surface pitch can be (512, 1024, 1536, 2048...)/4 (in Dwords)."
> 
> This patch adds the restriction for X tiling as well.
> 
> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
> Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  src/mesa/drivers/dri/i965/intel_blit.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)

Patch 6/8 is
Reviewed-by: Chad Versace <chad.versace at intel.com>