[Mesa-dev] [PATCH v5 18/70] i965/fs/nir: implement nir_intrinsic_get_buffer_size

[Samuel Iglesias Gonsálvez]

On 10/09/15 15:35, Iago Toral Quiroga wrote:
> From: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
> 
> Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
> ---
>  src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index a6c6a2f..3c55a12 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -1702,6 +1702,31 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
>        emit_barrier();
>        break;
>  
> +   case nir_intrinsic_get_buffer_size: {
> +      nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]);
> +      unsigned ubo_index = const_uniform_block ? const_uniform_block->u[0] : 0;
> +      int reg_width = dispatch_width / 8;
> +
> +      assert(shader->base.UniformBlocks[ubo_index].IsShaderStorage);
> +
> +      /* Set LOD = 0 */
> +      fs_reg source = fs_reg(0);
> +
> +      int mlen = 1 * reg_width;
> +      fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
> +                                  BRW_REGISTER_TYPE_UD);
> +      bld.LOAD_PAYLOAD(src_payload, &source, 1, 0);
> +
> +      fs_reg surf_index = fs_reg(prog_data->binding_table.ubo_start + ubo_index);
> +      fs_inst *inst = bld.emit(FS_OPCODE_GET_BUFFER_SIZE, dest,
> +                               src_payload, surf_index);
> +      inst->header_size = 0;
> +      inst->mlen = mlen;
> +      inst->regs_written = 4 * reg_width;

This is a mistake. The number of registers written by the instruction is
only one and resinfo returns the buffer size for SURFTYPE_BUFFER in x
component. For other surface types, it could write up to 4 components of
the same destination register.

I will fix it.

Sam

> +      bld.emit(inst);
> +      break;
> +   }
> +
>     default:
>        unreachable("unknown intrinsic");
>     }
>