[Mesa-dev] [PATCH 37/40] i965/blorp: Leave new batch signaling to batch buffer logic

Kenneth Graunke kenneth at whitecape.org
Fri Apr 22 06:08:53 UTC 2016


On Saturday, April 16, 2016 4:43:05 PM PDT Topi Pohjolainen wrote:
> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/
i965/brw_blorp.cpp
> index 1d3b3e2..04a2a74 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
> @@ -285,7 +285,8 @@ retry:
>        intel_batchbuffer_flush(brw);
>  
>     const uint64_t do_not_smash_bits = BRW_NEW_URB_SIZE |
> -                                      BRW_NEW_STATE_BASE_ADDRESS;
> +                                      BRW_NEW_STATE_BASE_ADDRESS |
> +                                      BRW_NEW_BATCH;
>  
>     /* We've smashed all state compared to what the normal 3D pipeline
>      * rendering tracks for GL.
> 

I don't think this is safe - it will cause a number of packets to not
be re-emitted even though BLORP clobbers them.

3DSTATE_VIEWPORT_STATE_POINTERS_CC:
 - clobbered by: gen7_blorp_emit_cc_viewport
 - uploaded by brw_cc_vp, _NEW_TRANSFORM | _NEW_VIEWPORT, BRW_NEW_BATCH

3DSTATE_DEPTH_BUFFER, HIER_DEPTH_BUFFER, STENCIL_BUFFER, CLEAR_PARAMS:
 - uploaded by gen7_depthbuffer: _NEW_BUFFERS | _NEW_DEPTH |
   _NEW_STENCIL, BRW_NEW_BATCH.

Renderbuffer Surfaces:
 - uploaded by gen6_renderbuffer_surfaces: _NEW_BUFFERS, BRW_NEW_BATCH

3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL, 3DSTATE_SCISSOR_STATE_POINTERS:
atom won't get re-emitted, but we don't clobber it so it should be fine
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