[Mesa-dev] [PATCH 1/3] i965/blorp: Instruct vertex fetcher to provide prim instance id

[Topi Pohjolainen]

This will indicate target layer (Render Target Array Index) needed
for layered clears.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/gen6_blorp.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 07130b5..8db496d 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -98,8 +98,10 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
     * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
     * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
     *   dw0: Reserved, MBZ.
-    *   dw1: Render Target Array Index. The HiZ op does not use indexed
-    *        vertices, so set the dword to 0.
+    *   dw1: Render Target Array Index. Below vertex fetcher gets programmed
+    *        to assign this with primitive instance identifier which will be
+    *        used for layered clears. All other renders have only one instance
+    *        and therefore the value will be effectively zero.
     *   dw2: Viewport Index. The HiZ op disables viewport mapping and
     *        scissoring, so set the dword to 0.
     *   dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
@@ -113,7 +115,7 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
     * "Vertex URB Entry (VUE) Formats".
     *
     * Only vertex position X and Y are going to be variable, Z is fixed to
-    * zero and W to one. Header words dw0-3 are all zero. There is no need to
+    * zero and W to one. Header words dw0,2,3 are zero. There is no need to
     * include the fixed values in the vertex buffer. Vertex fetcher can be
     * instructed to fill vertex elements with constant values of one and zero
     * instead of reading them from the buffer. See the vertex element setup
@@ -154,7 +156,7 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
                 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT |
                 0 << BRW_VE0_SRC_OFFSET_SHIFT);
       OUT_BATCH(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT |
-                BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT |
+                BRW_VE1_COMPONENT_STORE_IID << BRW_VE1_COMPONENT_1_SHIFT |
                 BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT |
                 BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT);
       /* Element 1 */
-- 
2.5.5