[Mesa-dev] [PATCH 2/3] i965/blorp: Add means to use normal render surface setup
Topi Pohjolainen
topi.pohjolainen at intel.com
Thu Apr 28 11:12:19 UTC 2016
This will be initially used for clears (allowing correct setup for
layered clears), and later on for blits that get launched against
the current gl-state.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 1 +
src/mesa/drivers/dri/i965/brw_blorp.h | 1 +
src/mesa/drivers/dri/i965/gen6_blorp.c | 11 +++++++++--
src/mesa/drivers/dri/i965/gen7_blorp.c | 11 +++++++++--
src/mesa/drivers/dri/i965/gen8_blorp.c | 11 ++++++++---
5 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 247fd75..b34dd03 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -49,6 +49,7 @@ brw_blorp_surface_info_init(struct brw_context *brw,
intel_miptree_check_level_layer(mt, level, layer);
info->mt = mt;
+ info->rb = NULL;
info->level = level;
info->layer = layer;
info->width = minify(mt->physical_width0, level - mt->first_level);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index c5c2c4e..0a4ac59 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -69,6 +69,7 @@ enum {
struct brw_blorp_surface_info
{
struct intel_mipmap_tree *mt;
+ struct gl_renderbuffer *rb;
/**
* The miplevel to use.
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 8db496d..8016cc7 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -1006,8 +1006,15 @@ gen6_blorp_exec(struct brw_context *brw,
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
- intel_miptree_used_for_rendering(params->dst.mt);
- wm_surf_offset_renderbuffer =
+
+ if (params->dst.mt)
+ intel_miptree_used_for_rendering(params->dst.mt);
+
+ wm_surf_offset_renderbuffer = params->dst.rb ?
+ brw->vtbl.update_renderbuffer_surface(brw, params->dst.rb,
+ false /* unused */,
+ 0 /* unused */,
+ ~0 /* surf index */) :
gen6_blorp_emit_surface_state(brw, params, ¶ms->dst,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c
index 8dc676b..0e7570d 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -832,8 +832,15 @@ gen7_blorp_exec(struct brw_context *brw,
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
- intel_miptree_used_for_rendering(params->dst.mt);
- wm_surf_offset_renderbuffer =
+
+ if (params->dst.mt)
+ intel_miptree_used_for_rendering(params->dst.mt);
+
+ wm_surf_offset_renderbuffer = params->dst.rb ?
+ brw->vtbl.update_renderbuffer_surface(brw, params->dst.rb,
+ false /* unused */,
+ 0 /* unused */,
+ ~0 /* surf index */) :
gen7_blorp_emit_surface_state(brw, ¶ms->dst,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER,
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c
index f1b2374..08c3526 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.c
@@ -590,9 +590,14 @@ gen8_blorp_emit_surface_states(struct brw_context *brw,
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
- intel_miptree_used_for_rendering(params->dst.mt);
-
- wm_surf_offset_renderbuffer =
+ if (params->dst.mt)
+ intel_miptree_used_for_rendering(params->dst.mt);
+
+ wm_surf_offset_renderbuffer = params->dst.rb ?
+ brw->vtbl.update_renderbuffer_surface(brw, params->dst.rb,
+ false /* unused */,
+ 0 /* unused */,
+ ~0 /* surf index */) :
gen8_blorp_emit_surface_state(brw, ¶ms->dst,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER,
--
2.5.5
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