[Mesa-dev] [PATCH 25/95] i965/vec4: fix base offset for nir_registers with doubles

[Francisco Jerez]

Iago Toral Quiroga <itoral at igalia.com> writes:

> ---
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index cf35f2e..fde7b60 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -280,7 +280,8 @@ vec4_visitor::get_nir_dest(const nir_dest &dest)
>        nir_ssa_values[dest.ssa.index] = dst;
>        return dst;
>     } else {
> -      return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
> +      unsigned base_offset = dest.reg.base_offset * dest.reg.reg->bit_size / 32;
> +      return dst_reg_for_nir_reg(this, dest.reg.reg, base_offset,
>                                   dest.reg.indirect);
>     }
>  }
> @@ -308,8 +309,9 @@ vec4_visitor::get_nir_src(const nir_src &src, enum brw_reg_type type,
>        reg = nir_ssa_values[src.ssa->index];
>     }
>     else {
> -     reg = dst_reg_for_nir_reg(this, src.reg.reg, src.reg.base_offset,
> -                               src.reg.indirect);
> +      unsigned base_offset = src.reg.base_offset * src.reg.reg->bit_size / 32;
> +      reg = dst_reg_for_nir_reg(this, src.reg.reg, base_offset,
> +                                src.reg.indirect);

I think this wouldn't have been necessary if you had fixed the offset()
helper to take into account the register type (as it does in the FS
back-end)?

>     }
>  
>     reg = retype(reg, type);
> -- 
> 2.7.4
>
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