[Mesa-dev] [PATCH 2/4] winsys/amdgpu: finish up SI addrlib integration

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 30 +++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 60c3cb9..69270f1 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -362,21 +362,22 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
    AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
    AddrSurfInfoIn.flags.degrade4Space = 1;
 
    /* DCC notes:
     * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
     *   with samples >= 4.
     * - Mipmapped array textures have low performance (discovered by a closed
     *   driver team).
     */
-   AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
+   AddrSurfInfoIn.flags.dccCompatible = ws->info.chip_class >= VI &&
+                                        !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
                                         !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
                                         !compressed && AddrDccIn.numSamples <= 1 &&
                                         ((surf->array_size == 1 && surf->npix_z == 1) ||
                                          surf->last_level == 0);
 
    AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
    AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
 
    /* noStencil = 0 can result in a depth part that is incompatible with
     * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
@@ -407,24 +408,43 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
        * the tile index, because we are expected to know it if
        * we know the other parameters.
        *
        * This is something that can easily be fixed in Addrlib.
        * For now, just figure it out here.
        * Note that only 2D_TILE_THIN1 is handled here.
        */
       assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
       assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
 
-      if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
-         AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
-      else
-         AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
+      if (ws->info.chip_class == SI) {
+         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
+            if (surf->bpe == 2)
+               AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
+            else
+               AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
+         } else {
+            if (surf->bpe == 1)
+               AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
+            else if (surf->bpe == 2)
+               AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
+            else if (surf->bpe == 4)
+               AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
+            else
+               AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
+         }
+      } else {
+         /* CIK - VI */
+         if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
+            AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
+         else
+            AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
+      }
    }
 
    surf->bo_size = 0;
    surf->dcc_size = 0;
    surf->dcc_alignment = 1;
 
    /* Calculate texture layout information. */
    for (level = 0; level <= surf->last_level; level++) {
       r = compute_level(ws, surf, false, level, type, compressed,
                         &AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut);
-- 
2.7.4