[Mesa-dev] [PATCH 1/4] winsys/amdgpu: initial SI support

[Alex Deucher]

On Mon, Aug 22, 2016 at 4:20 PM, Marek Olšák <maraeo at gmail.com> wrote:
> On Mon, Aug 22, 2016 at 5:00 PM, Alex Deucher <alexdeucher at gmail.com> wrote:
>> On Fri, Aug 19, 2016 at 5:11 AM, Marek Olšák <maraeo at gmail.com> wrote:
>>> From: Ronie Salgado <roniesalg at gmail.com>
>>>
>>> ---
>>>  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c      | 18 ++++++++++++++----
>>>  src/gallium/winsys/amdgpu/drm/amdgpu_surface.c |  9 +++++++--
>>>  src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c  | 25 +++++++++++++++++++++++++
>>>  3 files changed, 46 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
>>> index b171cc5..bf3e306 100644
>>> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
>>> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
>>> @@ -973,27 +973,37 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
>>>  {
>>>     struct amdgpu_cs *cs = amdgpu_cs(rcs);
>>>     struct amdgpu_winsys *ws = cs->ctx->ws;
>>>     int error_code = 0;
>>>
>>>     rcs->current.max_dw += amdgpu_cs_epilog_dws(cs->ring_type);
>>>
>>>     switch (cs->ring_type) {
>>>     case RING_DMA:
>>>        /* pad DMA ring to 8 DWs */
>>> -      while (rcs->current.cdw & 7)
>>> -         OUT_CS(rcs, 0x00000000); /* NOP packet */
>>> +      if (ws->info.chip_class <= SI) {
>>> +         while (rcs->current.cdw & 7)
>>> +            OUT_CS(rcs, 0xf0000000); /* NOP packet */
>>> +      } else {
>>> +         while (rcs->current.cdw & 7)
>>> +            OUT_CS(rcs, 0x00000000); /* NOP packet */
>>> +      }
>>>        break;
>>>     case RING_GFX:
>>>        /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
>>> -      while (rcs->current.cdw & 7)
>>> -         OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
>>> +      if (ws->info.gfx_ib_pad_with_type2) {
>>
>> Do we need gfx_ib_pad_with_type2?  Can we just check
>> ws->info.chip_class <= SI here?  That would be cleaner and more
>> consistent IMHO.
>
> Yeah, it would be somewhat cleaner from the winsys point of view.
> However, radeonsi already uses gfx_ib_pad_with_type2 for padding IBs
> within an IB.

Ah, ok, I didn't realize it was already used elsewhere.

>
> Maybe we can pad IBs with type3 unconditionally? Does the latest
> firmware support that? (if we used the latest firmware, that is)

You'll have to double check with the CP guys, but I don't think the
new type3 single dw nop is supported on SI.  I think the motivation
for it was actually for compute (CIK+ has separate MEC engines, SI is
still unified).  They didn't want to support type2 packets on the MEC.

Alex