[Mesa-dev] [PATCH 1/2] gallium: add cap to export device pointer size

[Ilia Mirkin]

Please add documentation for this new cap in
src/gallium/docs/source/screen.rst . What is this supposed to
represent btw? All G80+ GPUs operate in a 40-bit virtual address
space, but pre-fermi there's no ability to get a compute shader to
access more than a 32-bit window at a time (actually 16 such windows,
I believe, effectively getting it to 36-bit). Fermi+ GPUs are,
however, able to operate with both 32- and 64-bit pointers. (I forget
what happens if you use a 32-bit pointer... I think the upper word
might be pre-configured to a fixed value somewhere.)

On Sun, Aug 28, 2016 at 1:12 PM, Jan Vesely <jan.vesely at rutgers.edu> wrote:
> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
> ---
>  src/gallium/drivers/ilo/ilo_screen.c           | 6 ++++++
>  src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++
>  src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++
>  src/gallium/drivers/radeon/r600_pipe_common.c  | 8 ++++++++
>  src/gallium/drivers/softpipe/sp_screen.c       | 1 +
>  src/gallium/include/pipe/p_defines.h           | 1 +
>  6 files changed, 20 insertions(+)
>
> diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c
> index 050c03b..b9e5ad6 100644
> --- a/src/gallium/drivers/ilo/ilo_screen.c
> +++ b/src/gallium/drivers/ilo/ilo_screen.c
> @@ -199,6 +199,7 @@ ilo_get_compute_param(struct pipe_screen *screen,
>        uint32_t max_compute_units;
>        uint32_t images_supported;
>        uint32_t subgroup_size;
> +      uint32_t address_bits;
>     } val;
>     const void *ptr;
>     int size;
> @@ -266,6 +267,11 @@ ilo_get_compute_param(struct pipe_screen *screen,
>        ptr = &val.max_input_size;
>        size = sizeof(val.max_input_size);
>        break;
> +   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
> +      val.address_bits = 32;
> +      ptr = &val.address_bits;
> +      size = sizeof(val.address_bits);
> +      break;
>     case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
>        val.max_mem_alloc_size = 1u << 31;
>
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> index d878547..57c0c2b 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> @@ -418,6 +418,8 @@ nv50_screen_get_compute_param(struct pipe_screen *pscreen,
>        RET((uint32_t []) { screen->mp_count });
>     case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
>        RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
> +   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
> +      RET((uint32_t []) { 32 });
>     default:
>        return 0;
>     }
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index f139f66..e7bfbbe 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -479,6 +479,8 @@ nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
>        RET((uint32_t []) { screen->mp_count_compute });
>     case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
>        RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
> +   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
> +      RET((uint32_t []) { 64 });
>     default:
>        return 0;
>     }
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
> index b1da22f..1b15594 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -881,6 +881,14 @@ static int r600_get_compute_param(struct pipe_screen *screen,
>                                 *max_threads_per_block = 256;
>                 }
>                 return sizeof(uint64_t);
> +       case PIPE_COMPUTE_CAP_ADDRESS_BITS:
> +               if (ret) {
> +                       uint32_t *address_bits = ret;
> +                       address_bits[0] = 32;
> +                       if (rscreen->chip_class >= SI)
> +                               address_bits[0] = 64;
> +               }
> +               return 1 * sizeof(uint32_t);
>
>         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
>                 if (ret) {
> diff --git a/src/gallium/drivers/softpipe/sp_screen.c b/src/gallium/drivers/softpipe/sp_screen.c
> index b742bde..cd4269f 100644
> --- a/src/gallium/drivers/softpipe/sp_screen.c
> +++ b/src/gallium/drivers/softpipe/sp_screen.c
> @@ -521,6 +521,7 @@ softpipe_get_compute_param(struct pipe_screen *_screen,
>     case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
>     case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
>     case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
> +   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
>        break;
>     }
>     return 0;
> diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
> index 1e4d802..5361ed6 100644
> --- a/src/gallium/include/pipe/p_defines.h
> +++ b/src/gallium/include/pipe/p_defines.h
> @@ -834,6 +834,7 @@ enum pipe_shader_ir
>   */
>  enum pipe_compute_cap
>  {
> +   PIPE_COMPUTE_CAP_ADDRESS_BITS,
>     PIPE_COMPUTE_CAP_IR_TARGET,
>     PIPE_COMPUTE_CAP_GRID_DIMENSION,
>     PIPE_COMPUTE_CAP_MAX_GRID_SIZE,
> --
> 2.7.4
>