[Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

[Francisco Jerez]

Samuel Iglesias Gonsálvez <siglesias at igalia.com> writes:

> On Tue, 2016-12-13 at 09:01 +0100, Samuel Iglesias Gonsálvez wrote:
>> 
> [...]
>> > i965/vec4/nir: implement double comparisons
>> > 
>> > 	Trivial: A newline before the if() would be nice.
>> > 
>> > 	I have a memory of Curro telling me that the hardware maps each
>> > 	32-bit chunk in the dst to a single bit in the flag register.
>> > 	Maybe that's only on IVB, and maybe I'm misremembering. I'm
>> > 	concerned that while the PICK_LOW+MOV will properly handle the
>> > 	result that is written to the destination, the result written
>> > to
>> > 	the flag register might be incorrect.
>> > 
>> > 	My commit d9b09f8a30 fixed some problems that seems similar in
>> > 	my mind.
>> > 
>> 
>> As far as we know that is not what happens, and the flag register has
>> one bit for each logical channel (so each 64-bit chunk for DF
>> instructions). If that were not the case, I'd expect a lot of the
>> tests
>> for doubles to fail or at least non-uniform control-flow scenarios to
>> fail, for which we have specific tests that are passing just fine in
>> both haswell and ivybridge. We will try to double-check with Curro
>> just
>> in case though.
>> 
>
> We have just found an old email from Curro saying that it works as we
> think (one bit per logical channel). Maybe Curro wants to confirm it (I
> added him on Cc).
>

The only case I can recall where a DF instruction will interpret the
flag register incorrectly (as two bits per channel instead of one bit
per channel) only affects the decompression logic of the SEL
instruction, and only in Align16 mode (sigh...) -- I don't think your
double float comparison code will be affected.

> Sam
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