[Mesa-dev] [PATCH 6/6] gallium/radeon: rename winsys buffer_get/set_tiling to buffer_get/set_metadata
Marek Olšák
maraeo at gmail.com
Wed Feb 24 23:09:10 UTC 2016
From: Marek Olšák <marek.olsak at amd.com>
and rename the structure.
Later it will be extended to support amdgpu metadata.
---
src/gallium/drivers/r300/r300_texture.c | 8 ++---
src/gallium/drivers/radeon/r600_texture.c | 48 ++++++++++++-------------
src/gallium/drivers/radeon/radeon_winsys.h | 20 ++++++-----
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 50 +++++++++++++--------------
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 12 +++----
5 files changed, 70 insertions(+), 68 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
index 3f4c662..3adee8e 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1005,7 +1005,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
{
struct radeon_winsys *rws = rscreen->rws;
struct r300_resource *tex = NULL;
- struct radeon_bo_tiling_info tiling = {};
+ struct radeon_bo_metadata tiling = {};
tex = CALLOC_STRUCT(r300_resource);
if (!tex) {
@@ -1063,7 +1063,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
tiling.microtile = tex->tex.microtile;
tiling.macrotile = tex->tex.macrotile[0];
tiling.stride = tex->tex.stride_in_bytes[0];
- rws->buffer_set_tiling(tex->buf, &tiling);
+ rws->buffer_set_metadata(tex->buf, &tiling);
return tex;
@@ -1104,7 +1104,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen,
struct radeon_winsys *rws = rscreen->rws;
struct pb_buffer *buffer;
unsigned stride;
- struct radeon_bo_tiling_info tiling = {};
+ struct radeon_bo_metadata tiling = {};
/* Support only 2D textures without mipmaps */
if ((base->target != PIPE_TEXTURE_2D &&
@@ -1118,7 +1118,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen,
if (!buffer)
return NULL;
- rws->buffer_get_tiling(buffer, &tiling);
+ rws->buffer_get_metadata(buffer, &tiling);
/* Enforce a microtiled zbuffer. */
if (util_format_is_depth_or_stencil(base->format) &&
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index e181557..1e0117d 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -236,23 +236,23 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
struct r600_resource *resource = &rtex->resource;
struct radeon_surf *surface = &rtex->surface;
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
- struct radeon_bo_tiling_info tiling = {};
+ struct radeon_bo_metadata metadata = {};
- tiling.microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
+ metadata.microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
- tiling.macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
+ metadata.macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
- tiling.pipe_config = surface->pipe_config;
- tiling.bankw = surface->bankw;
- tiling.bankh = surface->bankh;
- tiling.tile_split = surface->tile_split;
- tiling.stencil_tile_split = surface->stencil_tile_split;
- tiling.mtilea = surface->mtilea;
- tiling.num_banks = surface->num_banks;
- tiling.stride = surface->level[0].pitch_bytes;
- tiling.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
-
- rscreen->ws->buffer_set_tiling(resource->buf, &tiling);
+ metadata.pipe_config = surface->pipe_config;
+ metadata.bankw = surface->bankw;
+ metadata.bankh = surface->bankh;
+ metadata.tile_split = surface->tile_split;
+ metadata.stencil_tile_split = surface->stencil_tile_split;
+ metadata.mtilea = surface->mtilea;
+ metadata.num_banks = surface->num_banks;
+ metadata.stride = surface->level[0].pitch_bytes;
+ metadata.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
+
+ rscreen->ws->buffer_set_metadata(resource->buf, &metadata);
return rscreen->ws->buffer_get_handle(resource->buf,
surface->level[0].pitch_bytes, whandle);
@@ -888,7 +888,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
unsigned array_mode;
struct radeon_surf surface;
int r;
- struct radeon_bo_tiling_info tiling = {};
+ struct radeon_bo_metadata metadata = {};
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
@@ -899,17 +899,17 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
if (!buf)
return NULL;
- rscreen->ws->buffer_get_tiling(buf, &tiling);
+ rscreen->ws->buffer_get_metadata(buf, &metadata);
- surface.bankw = tiling.bankw;
- surface.bankh = tiling.bankh;
- surface.tile_split = tiling.tile_split;
- surface.stencil_tile_split = tiling.stencil_tile_split;
- surface.mtilea = tiling.mtilea;
+ surface.bankw = metadata.bankw;
+ surface.bankh = metadata.bankh;
+ surface.tile_split = metadata.tile_split;
+ surface.stencil_tile_split = metadata.stencil_tile_split;
+ surface.mtilea = metadata.mtilea;
- if (tiling.macrotile == RADEON_LAYOUT_TILED)
+ if (metadata.macrotile == RADEON_LAYOUT_TILED)
array_mode = RADEON_SURF_MODE_2D;
- else if (tiling.microtile == RADEON_LAYOUT_TILED)
+ else if (metadata.microtile == RADEON_LAYOUT_TILED)
array_mode = RADEON_SURF_MODE_1D;
else
array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
@@ -919,7 +919,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
return NULL;
}
- if (tiling.scanout)
+ if (metadata.scanout)
surface.flags |= RADEON_SURF_SCANOUT;
return (struct pipe_resource *)r600_texture_create_object(screen, templ,
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 572f8ef..334c125 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -276,7 +276,7 @@ struct radeon_info {
uint32_t cik_macrotile_mode_array[16];
};
-struct radeon_bo_tiling_info {
+struct radeon_bo_metadata {
enum radeon_bo_layout microtile;
enum radeon_bo_layout macrotile;
unsigned pipe_config;
@@ -468,22 +468,24 @@ struct radeon_winsys {
enum radeon_bo_usage usage);
/**
- * Return tiling flags describing a memory layout of a buffer object.
+ * Return buffer metadata.
+ * (tiling info for display code, DRI sharing, and other data)
*
* \param buf A winsys buffer object to get the flags from.
- * \param tiling Tiling info for display code and DRI sharing.
+ * \param md Metadata
*/
- void (*buffer_get_tiling)(struct pb_buffer *buf,
- struct radeon_bo_tiling_info *tiling);
+ void (*buffer_get_metadata)(struct pb_buffer *buf,
+ struct radeon_bo_metadata *md);
/**
- * Set tiling flags describing a memory layout of a buffer object.
+ * Set buffer metadata.
+ * (tiling info for display code, DRI sharing, and other data)
*
* \param buf A winsys buffer object to set the flags for.
- * \param tiling Tiling info for display code and DRI sharing.
+ * \param md Metadata
*/
- void (*buffer_set_tiling)(struct pb_buffer *buf,
- struct radeon_bo_tiling_info *tiling);
+ void (*buffer_set_metadata)(struct pb_buffer *buf,
+ struct radeon_bo_metadata *md);
/**
* Get a winsys buffer from a winsys handle. The internal structure
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 8282ec9..10ac2b2 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -390,8 +390,8 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split)
}
}
-static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
- struct radeon_bo_tiling_info *tiling)
+static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf,
+ struct radeon_bo_metadata *md)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_bo_info info = {0};
@@ -404,44 +404,44 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
tiling_flags = info.metadata.tiling_info;
- tiling->microtile = RADEON_LAYOUT_LINEAR;
- tiling->macrotile = RADEON_LAYOUT_LINEAR;
+ md->microtile = RADEON_LAYOUT_LINEAR;
+ md->macrotile = RADEON_LAYOUT_LINEAR;
if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
- tiling->macrotile = RADEON_LAYOUT_TILED;
+ md->macrotile = RADEON_LAYOUT_TILED;
else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
- tiling->microtile = RADEON_LAYOUT_TILED;
+ md->microtile = RADEON_LAYOUT_TILED;
- tiling->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
- tiling->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
- tiling->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
- tiling->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
- tiling->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */
+ md->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
+ md->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
+ md->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
+ md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
+ md->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */
}
-static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
- struct radeon_bo_tiling_info *tiling)
+static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf,
+ struct radeon_bo_metadata *md)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_bo_metadata metadata = {0};
uint32_t tiling_flags = 0;
- if (tiling->macrotile == RADEON_LAYOUT_TILED)
+ if (md->macrotile == RADEON_LAYOUT_TILED)
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
- else if (tiling->microtile == RADEON_LAYOUT_TILED)
+ else if (md->microtile == RADEON_LAYOUT_TILED)
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
else
tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
- tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, tiling->pipe_config);
- tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(tiling->bankw));
- tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(tiling->bankh));
- if (tiling->tile_split)
- tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(tiling->tile_split));
- tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(tiling->mtilea));
- tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(tiling->num_banks)-1);
+ tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->pipe_config);
+ tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->bankw));
+ tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->bankh));
+ if (md->tile_split)
+ tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(md->tile_split));
+ tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea));
+ tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->num_banks)-1);
- if (tiling->scanout)
+ if (md->scanout)
tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */
else
tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */
@@ -702,8 +702,8 @@ static uint64_t amdgpu_bo_get_va(struct pb_buffer *buf)
void amdgpu_bo_init_functions(struct amdgpu_winsys *ws)
{
- ws->base.buffer_set_tiling = amdgpu_bo_set_tiling;
- ws->base.buffer_get_tiling = amdgpu_bo_get_tiling;
+ ws->base.buffer_set_metadata = amdgpu_buffer_set_metadata;
+ ws->base.buffer_get_metadata = amdgpu_buffer_get_metadata;
ws->base.buffer_map = amdgpu_bo_map;
ws->base.buffer_unmap = amdgpu_bo_unmap;
ws->base.buffer_wait = amdgpu_bo_wait;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index fd7cba5..1772a7c 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -636,8 +636,8 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split)
}
}
-static void radeon_bo_get_tiling(struct pb_buffer *_buf,
- struct radeon_bo_tiling_info *tiling)
+static void radeon_bo_get_metadata(struct pb_buffer *_buf,
+ struct radeon_bo_metadata *tiling)
{
struct radeon_bo *bo = radeon_bo(_buf);
struct drm_radeon_gem_set_tiling args;
@@ -670,8 +670,8 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf,
tiling->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT);
}
-static void radeon_bo_set_tiling(struct pb_buffer *_buf,
- struct radeon_bo_tiling_info *tiling)
+static void radeon_bo_set_metadata(struct pb_buffer *_buf,
+ struct radeon_bo_metadata *tiling)
{
struct radeon_bo *bo = radeon_bo(_buf);
struct drm_radeon_gem_set_tiling args;
@@ -1040,8 +1040,8 @@ static uint64_t radeon_winsys_bo_va(struct pb_buffer *buf)
void radeon_drm_bo_init_functions(struct radeon_drm_winsys *ws)
{
- ws->base.buffer_set_tiling = radeon_bo_set_tiling;
- ws->base.buffer_get_tiling = radeon_bo_get_tiling;
+ ws->base.buffer_set_metadata = radeon_bo_set_metadata;
+ ws->base.buffer_get_metadata = radeon_bo_get_metadata;
ws->base.buffer_map = radeon_bo_map;
ws->base.buffer_unmap = radeon_bo_unmap;
ws->base.buffer_wait = radeon_bo_wait;
--
2.5.0
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