[Mesa-dev] [v3 1/5] i965/gen9: Prepare surface state setup for lossless compression

[Topi Pohjolainen]

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression (intel_miptree_is_lossless_compressed()).
v3 (Ben): Do not set fast claer state in surface state setup.
          Moved into brw_postdraw_set_buffers_need_resolve()
          using a separate patch.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_defines.h        | 1 +
 src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 60b696c..3193d32 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -656,6 +656,7 @@
 #define GEN8_SURFACE_AUX_MODE_MCS               1
 #define GEN8_SURFACE_AUX_MODE_APPEND            2
 #define GEN8_SURFACE_AUX_MODE_HIZ               3
+#define GEN9_SURFACE_AUX_MODE_CCS_E             5
 
 /* Surface state DW7 */
 #define GEN9_SURFACE_RT_COMPRESSION_SHIFT       30
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 0a52815..8631c90 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -216,6 +216,9 @@ gen8_get_aux_mode(const struct brw_context *brw,
    if (brw->gen >= 9 || mt->num_samples == 1)
       assert(mt->halign == 16);
 
+   if (intel_miptree_is_lossless_compressed(brw, mt))
+      return GEN9_SURFACE_AUX_MODE_CCS_E;
+
    return GEN8_SURFACE_AUX_MODE_MCS;
 }
 
-- 
2.5.0