[Mesa-dev] [PATCH 2/6] i965/gen8+: Invalidate color calc state when switching to the GPGPU pipeline.

[Matt Turner]

On Sun, Jan 3, 2016 at 1:48 AM, Francisco Jerez <currojerez at riseup.net> wrote:
> This hardware bug can cause a hang on context restore while the
> current pipeline is set to GPGPU (BDWGFX HSD 1909593).  In addition to
> clearing the valid bit, mark the CC state as dirty to make sure that
> the CC indirect state pointer is re-emitted when we switch back to the
> 3D pipeline.
> ---
>  src/mesa/drivers/dri/i965/brw_misc_state.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index cf6ba5b..7d53d18 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -868,6 +868,26 @@ brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
>     const uint32_t _3DSTATE_PIPELINE_SELECT =
>        is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
>
> +   if (brw->gen >= 8) {
> +      /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
> +       * PIPELINE_SELECT [DevBWR+]":
> +       *
> +       *   Project: BDW, SKL

I think we should restrict this block to brw->gen == 8 || brw->gen ==
9 in that case?

I can't find evidence that the workaround applies to later hardware
(and in fact the page cited has a different workaround for a later
generation).