[Mesa-dev] [PATCH 4/6] i965/gen4-5: Emit MI_FLUSH as required prior to switching pipelines.

[Kenneth Graunke]

On Saturday, January 2, 2016 10:48:03 PM PST Francisco Jerez wrote:
> AFAIK brw_emit_select_pipeline() is only called once during context
> init on Gen4-5, at which point the pipeline is likely to be already
> idle so it may just happen to work by luck regardless of the MI_FLUSH.
> ---
>  src/mesa/drivers/dri/i965/brw_misc_state.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/
dri/i965/brw_misc_state.c
> index 75540c1..e5af1da 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -914,6 +914,19 @@ brw_emit_select_pipeline(struct brw_context *brw, enum 
brw_pipeline pipeline)
>                                    PIPE_CONTROL_STATE_CACHE_INVALIDATE |
>                                    PIPE_CONTROL_INSTRUCTION_INVALIDATE |
>                                    PIPE_CONTROL_NO_WRITE);
> +
> +   } else {
> +      /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
> +       * PIPELINE_SELECT [DevBWR+]":
> +       *
> +       *   Project: PRE-DEVSNB
> +       *
> +       *   Software must ensure the current pipeline is flushed via an
> +       *   MI_FLUSH or PIPE_CONTROL prior to the execution of 
PIPELINE_SELECT.
> +       */
> +      BEGIN_BATCH(1);
> +      OUT_BATCH(MI_FLUSH);
> +      ADVANCE_BATCH();
>     }
>  
>     /* Select the pipeline */
> 

Patches 4-5 are:
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

Patch 6 already has Matt's review, so I'm going to leave it be.
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