[Mesa-dev] [PATCH 8/9] nir: Add code to fixup bitfield_insert/extract.

[Matt Turner]

The OpenGL specifications for bitfieldInsert() and bitfieldExtract() says:

   The result will be undefined if <offset> or <bits> is negative, or if
   the sum of <offset> and <bits> is greater than the number of bits
   used to store the operand.

Therefore passing bits=32, offset=0 is legal and defined in GLSL.

But the earlier DX11/SM5 bfi/ibfe/ubfe opcodes are specified to accept a
bitfield width ranging from 0-31. As such, Intel and AMD instructions
read only the low 5 bits of the width operand, making them not able to
implement the GLSL-specified behavior directly.

This commit adds a pass that inserts code to implement the trivial cases
of <bits> = 32 as

   bitfieldInsert:
      bits > 31 ? insert : bitfieldInsert(base, insert, offset, bits)

   bitfieldExtract:
      bits > 31 ? value : bitfieldExtract(value, offset, bits)
---
 src/glsl/Makefile.am                              |  5 +++
 src/glsl/Makefile.sources                         |  1 +
 src/glsl/nir/nir.h                                |  2 ++
 src/glsl/nir/nir_fixup_bitfield_insert_extract.py | 40 +++++++++++++++++++++++
 4 files changed, 48 insertions(+)
 create mode 100644 src/glsl/nir/nir_fixup_bitfield_insert_extract.py

diff --git a/src/glsl/Makefile.am b/src/glsl/Makefile.am
index ba7af7c..33d28ec 100644
--- a/src/glsl/Makefile.am
+++ b/src/glsl/Makefile.am
@@ -46,6 +46,7 @@ EXTRA_DIST = tests glcpp/tests README TODO glcpp/README	\
 	nir/nir_algebraic.py				\
 	nir/nir_builder_opcodes_h.py			\
 	nir/nir_constant_expressions.py			\
+	nir/nir_fixup_bitfield_insert_extract.py	\
 	nir/nir_opcodes.py				\
 	nir/nir_opcodes_c.py				\
 	nir/nir_opcodes_h.py				\
@@ -265,6 +266,10 @@ nir/nir_opt_algebraic.c: nir/nir_opt_algebraic.py nir/nir_algebraic.py
 	$(MKDIR_GEN)
 	$(PYTHON_GEN) $(srcdir)/nir/nir_opt_algebraic.py > $@ || ($(RM) $@; false)
 
+nir/nir_fixup_bitfield_insert_extract.c: nir/nir_fixup_bitfield_insert_extract.py nir/nir_algebraic.py
+	$(MKDIR_GEN)
+	$(PYTHON_GEN) $(srcdir)/nir/nir_fixup_bitfield_insert_extract.py > $@ || ($(RM) $@; false)
+
 nir_tests_control_flow_tests_SOURCES =			\
 	nir/tests/control_flow_tests.cpp
 nir_tests_control_flow_tests_CFLAGS =			\
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index fd28f5c..bb79d84 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -13,6 +13,7 @@ LIBGLCPP_GENERATED_FILES = \
 NIR_GENERATED_FILES = \
 	nir/nir_builder_opcodes.h \
 	nir/nir_constant_expressions.c \
+	nir/nir_fixup_bitfield_insert_extract.c \
 	nir/nir_opcodes.c \
 	nir/nir_opcodes.h \
 	nir/nir_opt_algebraic.c
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 23aec69..4b97b5e 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -2064,6 +2064,8 @@ void nir_lower_to_source_mods(nir_shader *shader);
 
 bool nir_lower_gs_intrinsics(nir_shader *shader);
 
+bool nir_fixup_bitfield_insert_extract(nir_shader *shader);
+
 bool nir_normalize_cubemap_coords(nir_shader *shader);
 
 void nir_live_ssa_defs_impl(nir_function_impl *impl);
diff --git a/src/glsl/nir/nir_fixup_bitfield_insert_extract.py b/src/glsl/nir/nir_fixup_bitfield_insert_extract.py
new file mode 100644
index 0000000..21ff47c
--- /dev/null
+++ b/src/glsl/nir/nir_fixup_bitfield_insert_extract.py
@@ -0,0 +1,40 @@
+#! /usr/bin/env python
+#
+# Copyright (C) 2015 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+# IN THE SOFTWARE.
+
+import nir_algebraic
+
+fixup = [
+   (('bitfield_insert', 'base', 'insert', 'offset', 'bits'),
+    ('bcsel', ('ilt', 31, 'bits'), 'insert',
+              ('bitfield_insert', 'base', 'insert', 'offset', 'bits'))),
+
+   (('ibitfield_extract', 'value', 'offset', 'bits'),
+    ('bcsel', ('ilt', 31, 'bits'), 'value',
+              ('ibitfield_extract', 'value', 'offset', 'bits'))),
+
+   (('ubitfield_extract', 'value', 'offset', 'bits'),
+    ('bcsel', ('ult', 31, 'bits'), 'value',
+              ('ubitfield_extract', 'value', 'offset', 'bits'))),
+]
+
+print nir_algebraic.AlgebraicPass("nir_fixup_bitfield_insert_extract", fixup).render()
-- 
2.4.9