[Mesa-dev] [PATCH] tgsi: add MEMBAR opcode to handle memoryBarrier* GLSL intrinsics

[Marek Olšák]

Reviewed-by: Marek Olšák <marek.olsak at amd.com>

Marek

On Sun, Jan 17, 2016 at 6:26 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
> ---
>  src/gallium/auxiliary/tgsi/tgsi_info.c     |  2 +-
>  src/gallium/docs/source/tgsi.rst           | 17 +++++++++++++++++
>  src/gallium/include/pipe/p_shader_tokens.h |  2 +-
>  3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c
> index b270dd7..46b296f 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_info.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
> @@ -149,7 +149,7 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
>     { 1, 2, 0, 0, 0, 0, 0, COMP, "FSGE", TGSI_OPCODE_FSGE },
>     { 1, 2, 0, 0, 0, 0, 0, COMP, "FSLT", TGSI_OPCODE_FSLT },
>     { 1, 2, 0, 0, 0, 0, 0, COMP, "FSNE", TGSI_OPCODE_FSNE },
> -   { 0, 1, 0, 0, 0, 0, 1, NONE, "", 112 },      /* removed */
> +   { 0, 1, 0, 0, 0, 0, 0, OTHR, "MEMBAR", TGSI_OPCODE_MEMBAR },
>     { 0, 1, 0, 0, 0, 0, 0, NONE, "CALLNZ", TGSI_OPCODE_CALLNZ },
>     { 0, 1, 0, 0, 0, 0, 0, NONE, "", 114 },     /* removed */
>     { 0, 1, 0, 0, 0, 0, 0, NONE, "BREAKC", TGSI_OPCODE_BREAKC },
> diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
> index 7810a3e..489cbb0 100644
> --- a/src/gallium/docs/source/tgsi.rst
> +++ b/src/gallium/docs/source/tgsi.rst
> @@ -2372,6 +2372,23 @@ programs.
>    the program.  Results are unspecified if any of the remaining
>    threads terminates or never reaches an executed BARRIER instruction.
>
> +.. opcode:: MEMBAR - Memory barrier
> +
> +  ``MEMBAR type``
> +
> +  This opcode waits for the completion of all memory accesses based on
> +  the type passed in. The type is an immediate bitfield with the following
> +  meaning:
> +
> +  Bit 0: Shader storage buffers
> +  Bit 1: Atomic buffers
> +  Bit 2: Images
> +  Bit 3: Shared memory
> +  Bit 4: Thread group
> +
> +  These may be passed in in any combination. An implementation is free to not
> +  distinguish between these as it sees fit. However these map to all the
> +  possibilities made available by GLSL.
>
>  .. _atomopcodes:
>
> diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h
> index f300207..8f3a400 100644
> --- a/src/gallium/include/pipe/p_shader_tokens.h
> +++ b/src/gallium/include/pipe/p_shader_tokens.h
> @@ -420,7 +420,7 @@ struct tgsi_property_data {
>  #define TGSI_OPCODE_FSLT                110
>  #define TGSI_OPCODE_FSNE                111
>
> -                                /* gap */
> +#define TGSI_OPCODE_MEMBAR              112
>  #define TGSI_OPCODE_CALLNZ              113
>                                  /* gap */
>  #define TGSI_OPCODE_BREAKC              115
> --
> 2.4.10
>
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