[Mesa-dev] [PATCH 4/4] radeonsi: enable late VS allocation (v2)

[Nicolai Hähnle]

Patches 1, 2 & 4 are

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 19.01.2016 20:20, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
>   src/gallium/drivers/radeonsi/si_state.c | 21 +++++++++++++++++++--
>   1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index f005461..ca32f5c 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3742,8 +3742,25 @@ static void si_init_config(struct si_context *sctx)
>   		si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
>   		si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
>   		si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
> -		si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
> -		si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
> +
> +		if (sscreen->b.info.num_good_compute_units /
> +		    (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
> +			/* Too few available compute units per SH. Disallowing
> +			 * VS to run on CU0 could hurt us more than late VS
> +			 * allocation would help.
> +			 *
> +			 * LATE_ALLOC_VS = 2 is the highest safe number.
> +			 */
> +			si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
> +			si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
> +		} else {
> +			/* Set LATE_ALLOC_VS == 31. It should be less than
> +			 * the number of scratch waves. VS can't run on CU0.
> +			 */
> +			si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
> +			si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
> +		}
> +
>   		si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
>   	}
>
>