[Mesa-dev] [PATCH 1/4] radeonsi: allow using all CUs for tessellation and on-chip GS (v2)

[Nicolai Hähnle]

This series is

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 22.01.2016 09:18, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> v2: After more discussion with hw teams, the kernel already contains the
>      optimal settings allowing us to use all CUs.
> ---
>   src/gallium/drivers/radeonsi/si_state.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index a3ddee8..67b2835 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3701,9 +3701,9 @@ static void si_init_config(struct si_context *sctx)
>   	si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
>
>   	if (sctx->b.chip_class >= CIK) {
> -		si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
> +		si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
>   		si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
> -		si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
> +		si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
>   		si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
>   		si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
>   		si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
>