[Mesa-dev] [PATCH] i965/skl: Utilize new 5th bit for gateway messages

[Matt Turner]

On Tue, Jan 26, 2016 at 3:44 PM, Ben Widawsky
<benjamin.widawsky at intel.com> wrote:
> Cc: Jordan Justen <jordan.l.justen at intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index aad512f..820c1d4 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -924,6 +924,8 @@ void
>  fs_visitor::emit_barrier()
>  {
>     assert(devinfo->gen >= 7);
> +   const uint32_t barrier_id_mask =
> +      devinfo->gen >= 9 ? 0x8f000000u : 0x0f000000u;

I have no idea what this is intended to fix, but I can confirm that
the mask is right (the fifth bit is discontiguous -- bit 31) in both
the thread and message payloads.

For my future self: "GPGPU Thread R0 Header", "Message Payload [IVB+]"

>     /* We are getting the barrier ID from the compute shader header */
>     assert(stage == MESA_SHADER_COMPUTE);
> @@ -937,7 +939,7 @@ fs_visitor::emit_barrier()
>
>     /* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
>     fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
> -   pbld.AND(component(payload, 2), r0_2, brw_imm_ud(0x0f000000u));
> +   pbld.AND(component(payload, 2), r0_2, brw_imm_ud(barrier_id_mask));

With the comment corrected (how about just "Copy the barrier id from
r0.2 to the message payload reg.2"?) like Chris noted,

Reviewed-by: Matt Turner <mattst88 at gmail.com>