[Mesa-dev] [PATCH] i965/gen8: Enable hiz for all depth levels

[Ben Widawsky]

From: Jordan Justen <jordan.l.justen at intel.com>

After modifying the hiz buffer allocation and qpitch calculation, hiz
appears to work in all cases on gen8.

v2 by Ben: add GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR. From docs:
"If the depth buffer clear operation does clear the entire width and height of
the surface, then the “full surface clear” bit in 3DSTATE_WM_OP must be set to
1."
I'm very surprised that no regressions were spotted originally.

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com> (v1)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com> (v1)
Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com> (v2)
---

I am currently running perf data on this patch, but we might not see an
improvement (Jordan didn't last time around). However, I think using more HiZ is
general a good thing, and we should merge the patch unless we have perf
regressions.

Jenkins shows no regressions except on BXT where I have no data.
---
 src/mesa/drivers/dri/i965/gen8_depth_state.c  | 2 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 93100a0..a51e362 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -472,7 +472,7 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
       dw1 |= GEN8_WM_HZ_HIZ_RESOLVE;
       break;
    case GEN6_HIZ_OP_DEPTH_CLEAR:
-      dw1 |= GEN8_WM_HZ_DEPTH_CLEAR;
+      dw1 |= GEN8_WM_HZ_DEPTH_CLEAR | GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR;
       break;
    case GEN6_HIZ_OP_NONE:
       unreachable("Should not get here.");
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 108dd87..28f4dc4 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1547,7 +1547,7 @@ intel_miptree_level_enable_hiz(struct brw_context *brw,
 {
    assert(mt->hiz_buf);
 
-   if (brw->gen >= 8 || brw->is_haswell) {
+   if (brw->is_haswell) {
       uint32_t width = minify(mt->physical_width0, level);
       uint32_t height = minify(mt->physical_height0, level);
 
-- 
2.7.0