[Mesa-dev] [PATCH 08/12] radeonsi: don't enable DCC in the sampler if first_level doesn't have it

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

If first_level > 0 and DCC is disabled for that level, let's skip DCC
reads entirely.
---
 src/gallium/drivers/radeonsi/si_descriptors.c | 21 +++++++++++++++++----
 src/gallium/drivers/radeonsi/si_state.c       |  2 +-
 src/gallium/drivers/radeonsi/si_state.h       |  5 +++--
 3 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index a20adec..5b99a3f 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -295,10 +295,21 @@ static void si_sampler_views_begin_new_cs(struct si_context *sctx,
 			      RADEON_USAGE_READWRITE, RADEON_PRIO_DESCRIPTORS);
 }
 
+/* Set texture descriptor fields that can be changed by reallocations.
+ *
+ * \param tex			texture
+ * \param base_level_info	information of the level of BASE_ADDRESS
+ * \param base_level		the level of BASE_ADDRESS
+ * \param first_level		pipe_sampler_view.u.tex.first_level
+ * \param block_width		util_format_get_blockwidth()
+ * \param is_stencil		select between separate Z & Stencil
+ * \param state			descriptor to update
+ */
 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
 				    const struct radeon_surf_level *base_level_info,
-				    unsigned base_level, unsigned block_width,
-				    bool is_stencil, uint32_t *state)
+				    unsigned base_level, unsigned first_level,
+				    unsigned block_width, bool is_stencil,
+				    uint32_t *state)
 {
 	uint64_t va = tex->resource.gpu_address + base_level_info->offset;
 	unsigned pitch = base_level_info->nblk_x * block_width;
@@ -314,7 +325,7 @@ void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
 							     is_stencil));
 	state[4] |= S_008F20_PITCH(pitch - 1);
 
-	if (tex->dcc_offset && base_level_info->dcc_enabled) {
+	if (tex->dcc_offset && tex->surface.level[first_level].dcc_enabled) {
 		state[6] |= S_008F28_COMPRESSION_EN(1);
 		state[7] = (tex->resource.gpu_address +
 			    tex->dcc_offset +
@@ -350,6 +361,7 @@ static void si_set_sampler_view(struct si_context *sctx,
 			si_set_mutable_tex_desc_fields(rtex,
 						       rview->base_level_info,
 						       rview->base_level,
+						       rview->base.u.tex.first_level,
 						       rview->block_width,
 						       is_separate_stencil,
 						       desc);
@@ -611,7 +623,8 @@ static void si_set_shader_image(struct si_context *ctx,
 					   view->u.tex.last_layer,
 					   width, height, depth,
 					   desc, NULL);
-		si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level], level,
+		si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
+					       level, level,
 					       util_format_get_blockwidth(view->format),
 					       false, desc);
 	}
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index fb7b38c..39f5799 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3449,7 +3449,7 @@ static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
 				   res->width0, res->height0, res->depth0,
 				   desc, NULL);
 
-	si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0,
+	si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
 				       rtex->surface.blk_w, false, desc);
 
 	/* Clear the base address and set the relative DCC offset. */
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index e5795eb..68817b7 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -253,8 +253,9 @@ struct si_buffer_resources {
 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
 void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
 				    const struct radeon_surf_level *base_level_info,
-				    unsigned base_level, unsigned block_width,
-				    bool is_stencil, uint32_t *state);
+				    unsigned base_level, unsigned first_level,
+				    unsigned block_width, bool is_stencil,
+				    uint32_t *state);
 void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 			struct pipe_resource *buffer,
 			unsigned stride, unsigned num_records,
-- 
2.7.4