[Mesa-dev] [PATCH 12/12] radeonsi: allow MSAA resolving into a texture that has DCC enabled

[Nicolai Hähnle]

For the series:

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 07.06.2016 12:04, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> Since DCC is enabled almost everywhere now, it's important not to disable
> this fast path.
> ---
>   src/gallium/drivers/radeonsi/si_blit.c  | 15 +++++++++++++--
>   src/gallium/drivers/radeonsi/si_state.c | 12 ++++++++++--
>   2 files changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
> index 3f45256..5c7b318 100644
> --- a/src/gallium/drivers/radeonsi/si_blit.c
> +++ b/src/gallium/drivers/radeonsi/si_blit.c
> @@ -902,8 +902,19 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
>   	    info->src.box.height == dst_height &&
>   	    info->src.box.depth == 1 &&
>   	    dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
> -	    (!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be fast-cleared */
> -	    !dst->dcc_offset) {
> +	    (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
> +		/* Resolving into a surface with DCC is unsupported. Since
> +		 * it's being overwritten anyway, clear it to uncompressed.
> +		 * This is still the fastest codepath even with this clear.
> +		 */
> +		if (dst->dcc_offset &&
> +		    dst->surface.level[info->dst.level].dcc_enabled) {
> +			vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
> +					   0xFFFFFFFF);
> +			dst->dirty_level_mask &= ~(1 << info->dst.level);
> +		}
> +
> +		/* Resolve directly from src to dst. */
>   		si_blitter_begin(ctx, SI_COLOR_RESOLVE |
>   				 (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
>   		util_blitter_custom_resolve_color(sctx->blitter,
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 39f5799..2e8fc7f 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -2445,8 +2445,16 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
>   		}
>
>   		cb_color_info = cb->cb_color_info | tex->cb_color_info;
> -		if (tex->dcc_offset && cb->level_info->dcc_enabled)
> -			cb_color_info |= S_028C70_DCC_ENABLE(1);
> +
> +		if (tex->dcc_offset && cb->level_info->dcc_enabled) {
> +			bool is_msaa_resolve_dst = state->cbufs[0] &&
> +						   state->cbufs[0]->texture->nr_samples > 1 &&
> +						   state->cbufs[1] == &cb->base &&
> +						   state->cbufs[1]->texture->nr_samples <= 1;
> +
> +			if (!is_msaa_resolve_dst)
> +				cb_color_info |= S_028C70_DCC_ENABLE(1);
> +		}
>
>   		radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
>   					   sctx->b.chip_class >= VI ? 14 : 13);
>