[Mesa-dev] [Mesa-stable] [PATCH] i965/bxt: Add 2x6 variant

[Emil Velikov]

On 26 May 2016 at 20:03, Francisco Jerez <currojerez at riseup.net> wrote:
> Kristian Høgsberg <krh at bitplanet.net> writes:
>
>> On Thu, May 26, 2016 at 8:08 AM, Ben Widawsky <ben at bwidawsk.net> wrote:
>>> Cc: mesa-stable at lists.freedesktop.org
>>> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
>>
>> The numbers check out.
>>
>> Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
>>
>>> ---
>>>  include/pci_ids/i965_pci_ids.h              |  2 ++
>>>  src/mesa/drivers/dri/i965/brw_device_info.c | 22 ++++++++++++++++++++++
>>>  2 files changed, 24 insertions(+)
>>>
>>> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
>>> index bd645fa..fce00da 100644
>>> --- a/include/pci_ids/i965_pci_ids.h
>>> +++ b/include/pci_ids/i965_pci_ids.h
>>> @@ -162,4 +162,6 @@ CHIPSET(0x22B2, chv,     "Intel(R) HD Graphics (Cherryview)")
>>>  CHIPSET(0x22B3, chv,     "Intel(R) HD Graphics (Cherryview)")
>>>  CHIPSET(0x0A84, bxt,     "Intel(R) HD Graphics (Broxton)")
>>>  CHIPSET(0x1A84, bxt,     "Intel(R) HD Graphics (Broxton)")
>>> +CHIPSET(0x1A85, bxt_2x6, "Intel(R) HD Graphics (Broxton 2x6)")
>>>  CHIPSET(0x5A84, bxt,     "Intel(R) HD Graphics (Broxton)")
>>> +CHIPSET(0x5A85, bxt_2x6, "Intel(R) HD Graphics (Broxton 2x6)")
>>> diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
>>> index 3666190..77bbe78 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_device_info.c
>>> +++ b/src/mesa/drivers/dri/i965/brw_device_info.c
>>> @@ -401,6 +401,28 @@ static const struct brw_device_info brw_device_info_bxt = {
>>>     }
>>>  };
>>>
>>> +static const struct brw_device_info brw_device_info_bxt_2x6 = {
>>> +   GEN9_FEATURES,
>>> +   .is_broxton = 1,
>>> +   .gt = 1,
>>> +   .has_llc = false,
>>> +
>>> +   .num_slices = 1,
>>> +   .max_vs_threads = 56, /* XXX: guess */
>>> +   .max_hs_threads = 56, /* XXX: guess */
>>> +   .max_ds_threads = 56,
>>> +   .max_gs_threads = 56,
>>> +   .max_wm_threads = 64 * 2,
>>> +   .max_cs_threads = 6 * 6,
>>> +   .urb = {
>>> +      .size = 128,
>>> +      .min_vs_entries = 34,
>>> +      .max_vs_entries = 352,
>>> +      .max_hs_entries = 128,
>>> +      .max_ds_entries = 208,
>>> +      .max_gs_entries = 128,
>>> +   }
>>> +};
>
>
> For this part to work I believe you'll have to add a new L3
> configuration table to the driver because IIRC the 2x6 model has a
> completely different L3 layout with a single huge L3 bank instead of two
> banks as in the 3x6 model, otherwise the L3 programming code will use
> the CHV-like tables (which should work fine on the normal BXT) that I
> believe will leave almost half of the L3 cache unpartitioned on the 2x6
> model.  Because it only has one bank the L3 way size will also be
> different (I expect 2KB instead of 4KB), so our URB size calculation and
> URB setup will be most likely incorrect right now.
>
Gents do we have a follow up on the above topic/suggestion ?
Francisco, my humble take on your explanation is that this will lead
to underutilisation of the hardware. Do you think that the
miscalculation can cause crashes and/or rendering problems ?

Thanks
Emil