[Mesa-dev] [PATCH 09/18] i965: add component packing support for tcs

[Timothy Arceri]

---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index ccacfb5..dbb3638 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2680,6 +2680,9 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
       fs_reg tmp =
          fs_reg(VGRF, alloc.allocate(2 * iter_components), value.type);
 
+      unsigned first_component = nir_intrinsic_component(instr);
+      mask = mask << first_component;
+
       for (unsigned iter = 0; iter < num_iterations; iter++) {
          if (!is_64bit && mask != WRITEMASK_XYZW) {
             srcs[header_regs++] = brw_imm_ud(mask << 16);
@@ -2717,11 +2720,12 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
          }
 
          for (unsigned i = 0; i < iter_components; i++) {
-            if (!(mask & (1 << i)))
+            if (!(mask & (1 << (i + first_component))))
                continue;
 
             if (!is_64bit) {
-               srcs[header_regs + i] = offset(value, bld, BRW_GET_SWZ(swiz, i));
+               srcs[header_regs + i + first_component] =
+                  offset(value, bld, BRW_GET_SWZ(swiz, i));
             } else {
                /* We need to shuffle the 64-bit data to match the layout
                 * expected by our 32-bit URB write messages. We use a temporary
@@ -2744,7 +2748,8 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
          }
 
          unsigned mlen =
-            header_regs + (is_64bit ? 2 * iter_components : iter_components);
+            header_regs + (is_64bit ? 2 * iter_components : iter_components) +
+            first_component;
          fs_reg payload =
             bld.vgrf(BRW_REGISTER_TYPE_UD, mlen);
          bld.LOAD_PAYLOAD(payload, srcs, mlen, header_regs);
-- 
2.5.5