[Mesa-dev] [PATCH 00/64] i965: Start using ISL for filling out surface states
Jason Ekstrand
jason at jlekstrand.net
Sat Jun 11 16:02:15 UTC 2016
We would like to eventually start using ISL inside of the GL driver to
replace the fairly sprawling layout code in brw_tex_layout.c and
intel_mipmap_tree.c. However, that is a very big change that no one is
ready to make yet. A smaller change, I thought, would be to start using
ISL in blorp. In order to do that, I needed a function to get an isl_surf
from an intel_mipmap_tree. How do you test such a function to ensure that
it's working in all of the cases? Use ISL for emitting all surface states
on everything and run it through Jenkins of course! Hence this series.
This series is one of the most educational projects I've worked on in a
bit. It turns out there are a lot of subtlties in surface layout and I
found bugs in both the i965 and ISL state setup code. I've tried to keep
all of the functional changes contained to the first 8 or so patches which
only touch the GL driver. That way those fixes can be back-ported to
stable and are bisectable.
The next 20 patches or so are general ISL cleanups and fixes. If no one is
too opposed, I'd like to back-port the whole pile to 12.0. There are two
reasons for this: First, ISL is new and this is a substantial cleanup;
back-porting it will make back-porting will keep the initial release of ISL
cleaner and make back-porting other patches easier in the future. Second,
in the middle of the series are a couple of changes that fix some 850
Vulkan CTS tests on Haswell.
The next 9 patches add support to ISL for filling out surface states on
gen4, 4x, 5, and 6 as well as support for color compression. I'm not sure
if the CCS formats are 100% correct or of that's even the exact approach we
want to take. Chad, I'd like you to chip in here.
Finally, starting with blorp, we replace almost all of the surface state
setup code in i965 with paths based on ISL. For textures/renderbuffers we
delete 1 path for gen4-5, 3 for gen6, 4 for gen7, and 3 for gen8 along with
3 different paths for emitting buffer surfaces.
As far as review goes, I'd like to get the i965 bugfixes and ISL cleanups
landed soon-ish and back-ported for 12.0. Everything after that is a bit
more up-in-the-air. It won't be all that hard to rebase because it's mosly
just whole-sale replacing the code we have with new code.
Cc: Chad Versace <chad.versace at intel.com>
Cc: Nanley Chery <nanleychery at gmail.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Topi Pohjolainen <topi.pohjolainen at intel.com>
Jason Ekstrand (64):
i965: Drop Max3DTextureLevels to 512 on Sandy Bridge and prior
i965/blorp/gen8: Use the correct max level and layer in
emit_surface_states
i965/gen8: Use the qpitch from the aux_mt for AUX_QPITCH
i965/fs: Use a default Y coordinate of 0 for TXF on gen9+
i965: Remove fake W-tiled render target support
i965/gen4: Subtract 1 from buffer sizes
i965/gen7,8: Set SURFACE_IS_ARRAY for all non-3D texture types
i965/blorp: Only set src_z for gen8+ 3D textures
genxml/gen8,9: Prefix the multisample format enum with MSFMT
isl/state: Don't use designated initializers for the surface state
isl/state: Remove some unused fields
isl/state: Put surface format setup at the top
isl/state: Put all dimension setup together and towards the top
isl/state: Put pitch calculations together
isl/state: Return an extent3d from the halign/valign helper
isl/state: Refactor the per-gen isl_to_gen_h/valign tables
isl/state: Refactor the setup of clear colors
isl/state: Don't force-disable L2 bypass for everything
isl/state: Set SurfaceArray based on the surface dimension
isl/format: Mark R9G9B9E5 as containing 9-bit unsigned float channels
isl/state: Set the IntegerSurfaceFormat bit on Haswell
isl/state: Use the layout for computing qpitch rather than dimensions
isl/state: Only set cube face enables if usage includes CUBE_BIT
isl/state: Emit no-op mip tail setup on SKL
isl/state: Use TILEWALK_XMAJOR for linear surfaces on gen7
isl/state: Don't set SurfacePitch for gen9 1-D textures
isl/state: Add assertions for buffer surface restrictions
isl/state: Don't use designated initializers for buffer surface state
isl/state: Allow for full 31-bit buffer texture sizes
anv,isl: Lower storage image formats in anv
genxml: Put append counter fields before MCS in RENDER_SURFACE_STATE
on gen7
genxml: Add enough XML for gens 4, 4.5, and 5 to get SURFACE_STATE
genxml: Make X/Y Offset field of SURFACE_STATE a uint
genxml: Add macros and #includes for gens 4-6
isl: Add an ISL_DEV_IS_G4X macro
isl: Add support for filling out surface states all the way back to
gen4
isl: Add surface formats for on-MSAA CCS surfaces
isl/state: Add support for handling color control surfaces
isl/state: Add support for OffsetX/Y in surface state
i965/miptree: Add a helper for getting an isl_surf from a miptree
i965/miptree: Add a helper for getting the ISL clear color from a
miptree
i965/miptree: Add a helper for getting the aux isl_surf from a miptree
i965/blorp: Add a generic ISL-based surface state emit path
i965/blorp: Use the generic ISL path for renderbuffer surfaces on
gen8-9
i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen7
i965/blorp: Use the generic ISL path for texture surfaces on gen7
i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen6
i965/blorp: Use the generic ISL path for texture surfaces on gen6
i965/state: Add a helper for emitting a surface state using isl
i965/blorp: Use a generic ISL path for texture surfaces on gen8
i965/state: Use ISL for emitting image surfaces
i965/surface_state: Rename brw_update to gen4_update
i965/state: Add generic surface update functions based on ISL
i965/gen8: Use the generic ISL-based path for texture surfaces
i965/gen8: Use the generic ISL-based path for renderbuffer surfaces
i965/gen7: Use the generic ISL-based path for texture surfaces
i965/gen7: Use the generic ISL-based path for renderbuffer surfaces
i965/gen6: Use the generic ISL-based path for renderbuffer surfaces
i965/gen4-6: Use the generic ISL-based path for texture surfaces
isl/formats: Mark RAW as having a block size of 1 byte
i965/state: Account for the element size in emit_buffer_surface_state
i965: Use ISL for emitting buffer surface states
i965: Get rid of gen6_surface_state.c
i965/context: Remove some unnecessary vfuncs
src/intel/genxml/Makefile.am | 3 +
src/intel/genxml/Makefile.sources | 3 +
src/intel/genxml/gen4.xml | 52 +++
src/intel/genxml/gen45.xml | 56 +++
src/intel/genxml/gen5.xml | 56 +++
src/intel/genxml/gen6.xml | 4 +-
src/intel/genxml/gen7.xml | 8 +-
src/intel/genxml/gen75.xml | 8 +-
src/intel/genxml/gen8.xml | 8 +-
src/intel/genxml/gen9.xml | 8 +-
src/intel/genxml/genX_pack.h | 10 +-
src/intel/genxml/gen_macros.h | 15 +-
src/intel/isl/Makefile.am | 12 +
src/intel/isl/Makefile.sources | 13 +-
src/intel/isl/isl.c | 28 ++
src/intel/isl/isl.h | 29 ++
src/intel/isl/isl_format_layout.csv | 13 +-
src/intel/isl/isl_priv.h | 24 +
src/intel/isl/isl_surface_state.c | 462 +++++++++++--------
src/intel/vulkan/anv_image.c | 3 +
src/mesa/drivers/dri/i965/Makefile.sources | 1 -
src/mesa/drivers/dri/i965/brw_binding_tables.c | 2 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 146 ++++++
src/mesa/drivers/dri/i965/brw_blorp.h | 6 +
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 11 +-
src/mesa/drivers/dri/i965/brw_context.c | 5 +-
src/mesa/drivers/dri/i965/brw_context.h | 25 -
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +
src/mesa/drivers/dri/i965/brw_state.h | 55 ++-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 532 ++++++++++++++--------
src/mesa/drivers/dri/i965/gen6_blorp.c | 83 +---
src/mesa/drivers/dri/i965/gen6_surface_state.c | 146 ------
src/mesa/drivers/dri/i965/gen7_blorp.c | 105 +----
src/mesa/drivers/dri/i965/gen7_cs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 408 +----------------
src/mesa/drivers/dri/i965/gen8_blorp.c | 147 ++----
src/mesa/drivers/dri/i965/gen8_surface_state.c | 509 +--------------------
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 265 ++++++++++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 14 +
39 files changed, 1474 insertions(+), 1805 deletions(-)
create mode 100644 src/intel/genxml/gen4.xml
create mode 100644 src/intel/genxml/gen45.xml
create mode 100644 src/intel/genxml/gen5.xml
delete mode 100644 src/mesa/drivers/dri/i965/gen6_surface_state.c
--
2.5.0.400.gff86faf
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