[Mesa-dev] [PATCH] i965/fs: Fix regs_written for SIMD-lowered instructions some more.

[Jordan Justen]

Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

On 2016-06-10 22:39:23, Francisco Jerez wrote:
> ISTR having suggested this during review of the recent FP64 changes to
> the SIMD lowering pass, but it doesn't look like it was taken into
> account in the end.  Using the fs_reg::component_size helper instead
> of this open-coded variant makes sure that the stride is taken into
> account correctly.  Fixes at least the following piglit tests with
> spilling forced on (since otherwise regs_written would be calculated
> incorrectly and the spilling code would be rather confused about how
> much data needs to be spilled):
> 
>  spec.arb_gpu_shader_fp64.shader_storage.layout-std140-fp64-shader
>  spec.arb_gpu_shader_fp64.shader_storage.layout-std140-fp64-mixed-shader
> 
> Cc: <mesa-stable at lists.freedesktop.org>
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 104c20b..0347b0a 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -5261,9 +5261,9 @@ fs_visitor::lower_simd_width()
>                 split_inst.src[j] = emit_unzip(lbld, block, inst, j);
>  
>              split_inst.dst = emit_zip(lbld, block, inst);
> -            split_inst.regs_written =
> -               DIV_ROUND_UP(type_sz(inst->dst.type) * dst_size * lower_width,
> -                            REG_SIZE);
> +            split_inst.regs_written = DIV_ROUND_UP(
> +               split_inst.dst.component_size(lower_width) * dst_size,
> +               REG_SIZE);
>  
>              lbld.emit(split_inst);
>           }
> -- 
> 2.7.3
> 
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