[Mesa-dev] [PATCH 3/3] radeonsi: try to hit direct hw MSAA resolve by changing micro mode in clear

[Marek Olšák]

On Tue, Jun 14, 2016 at 12:41 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> On 13.06.2016 18:17, Marek Olšák wrote:
>>
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> We could also do MSAA resolve in a compute shader like Vulkan and remove
>> these workarounds.
>> ---
>>   src/gallium/drivers/radeon/r600_pipe_common.h |  1 +
>>   src/gallium/drivers/radeon/r600_texture.c     | 83
>> +++++++++++++++++++++++++++
>>   src/gallium/drivers/radeonsi/si_blit.c        | 20 ++++++-
>>   3 files changed, 103 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
>> b/src/gallium/drivers/radeon/r600_pipe_common.h
>> index 59962be..eb8a25a 100644
>> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
>> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
>> @@ -252,6 +252,7 @@ struct r600_texture {
>>         uint64_t                        dcc_offset; /* 0 = disabled */
>>         unsigned                        cb_color_info; /* fast clear
>> enable bit */
>>         unsigned                        color_clear_value[2];
>> +       unsigned
>> last_msaa_resolve_target_micro_mode;
>>
>>         /* Depth buffer compression and fast clear. */
>>         struct r600_htile_info          htile;
>> diff --git a/src/gallium/drivers/radeon/r600_texture.c
>> b/src/gallium/drivers/radeon/r600_texture.c
>> index 3368dc9..31544b6 100644
>> --- a/src/gallium/drivers/radeon/r600_texture.c
>> +++ b/src/gallium/drivers/radeon/r600_texture.c
>> @@ -1015,6 +1015,8 @@ r600_texture_create_object(struct pipe_screen
>> *screen,
>>          * This must be done after r600_setup_surface.
>>          * Applies to R600-Cayman. */
>>         rtex->non_disp_tiling = rtex->is_depth &&
>> rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
>> +       /* Applies to GCN. */
>> +       rtex->last_msaa_resolve_target_micro_mode =
>> rtex->surface.micro_tile_mode;
>>
>>         if (rtex->is_depth) {
>>                 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
>> @@ -1821,6 +1823,79 @@ void vi_dcc_clear_level(struct r600_common_context
>> *rctx,
>>                            clear_value, R600_COHERENCY_CB_META);
>>   }
>>
>> +/* Set the same micro tile mode as the destination of the last MSAA
>> resolve.
>> + * This allows hitting the MSAA resolve fast path, which requires that
>> both
>> + * src and dst micro tile modes match.
>> + */
>> +static void si_set_optimal_micro_tile_mode(struct r600_common_screen
>> *rscreen,
>> +                                          struct r600_texture *rtex)
>> +{
>> +       if (rtex->resource.is_shared ||
>> +           rtex->surface.nsamples <= 1 ||
>> +           rtex->surface.micro_tile_mode ==
>> rtex->last_msaa_resolve_target_micro_mode)
>> +               return;
>> +
>> +       assert(rtex->surface.level[0].mode == RADEON_SURF_MODE_2D);
>> +       assert(rtex->surface.last_level == 0);
>> +
>> +       if (rscreen->chip_class >= CIK) {
>> +               switch (rtex->last_msaa_resolve_target_micro_mode) {
>> +               case 0: /* displayable */
>> +                       rtex->surface.tiling_index[0] = 10;
>> +                       break;
>> +               case 1: /* thin */
>> +                       rtex->surface.tiling_index[0] = 14;
>> +                       break;
>> +               case 3: /* rotated */
>> +                       rtex->surface.tiling_index[0] = 28;
>> +                       break;
>> +               default: /* depth, thick */
>> +                       assert(!"unexpected micro mode");
>> +                       return;
>> +               }
>> +       } else { /* SI */
>> +               switch (rtex->last_msaa_resolve_target_micro_mode) {
>> +               case 0: /* displayable */
>> +                       switch (rtex->surface.bpe) {
>> +                       case 8:
>> +                            rtex->surface.tiling_index[0] = 10;
>> +                            break;
>> +                       case 16:
>> +                            rtex->surface.tiling_index[0] = 11;
>> +                            break;
>> +                       default: /* 32, 64 */
>> +                            rtex->surface.tiling_index[0] = 12;
>> +                            break;
>> +                       }
>> +                       break;
>> +               case 1: /* thin */
>> +                       switch (rtex->surface.bpe) {
>> +                       case 8:
>> +                                rtex->surface.tiling_index[0] = 14;
>> +                                break;
>> +                       case 16:
>> +                                rtex->surface.tiling_index[0] = 15;
>> +                                break;
>> +                       case 32:
>> +                                rtex->surface.tiling_index[0] = 16;
>> +                                break;
>> +                       default: /* 64, 128 */
>> +                                rtex->surface.tiling_index[0] = 17;
>> +                                break;
>> +                       }
>
>
> Are those magic numbers documented somewhere?

It's from addrlib. There are no definitions for them there. They are
all 2D_THIN modes with different bpp and micro tile mode. I can add
the definitions above the function if that's what you would like.

Marek