[Mesa-dev] [PATCH 05/27] i965: add component packing support for gs

[Timothy Arceri]

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_fs.h       |  2 +-
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 22 ++++++++++++++++++----
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index fc85206..0c72802 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -266,7 +266,7 @@ public:
    void emit_gs_thread_end();
    void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
                            unsigned base_offset, const nir_src &offset_src,
-                           unsigned num_components);
+                           unsigned num_components, unsigned first_component);
    void emit_cs_terminate();
    fs_reg *emit_cs_work_group_id_setup();
 
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 849a1c4..77355ff 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2005,7 +2005,8 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
                                const nir_src &vertex_src,
                                unsigned base_offset,
                                const nir_src &offset_src,
-                               unsigned num_components)
+                               unsigned num_components,
+                               unsigned first_component)
 {
    struct brw_gs_prog_data *gs_prog_data = (struct brw_gs_prog_data *) prog_data;
 
@@ -2139,11 +2140,23 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
    for (unsigned iter = 0; iter < num_iterations; iter++) {
       if (offset_const) {
          /* Constant indexing - use global offset. */
-         inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp_dst, icp_handle);
+         if (first_component != 0) {
+            unsigned read_components = num_components + first_component;
+            fs_reg tmp = bld.vgrf(dst.type, read_components);
+            inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp, icp_handle);
+            inst->regs_written = read_components;
+            for (unsigned i = 0; i < num_components; i++) {
+               bld.MOV(offset(tmp_dst, bld, i),
+                       offset(tmp, bld, i + first_component));
+            }
+         } else {
+            inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp_dst,
+                            icp_handle);
+            inst->regs_written = num_components * type_sz(tmp_dst.type) / 4;
+         }
          inst->offset = base_offset + offset_const->u32[0];
          inst->base_mrf = -1;
          inst->mlen = 1;
-         inst->regs_written = num_components * type_sz(tmp_dst.type) / 4;
       } else {
          /* Indirect indexing - use per-slot offsets as well. */
          const fs_reg srcs[] = { icp_handle, indirect_offset };
@@ -2916,7 +2929,8 @@ fs_visitor::nir_emit_gs_intrinsic(const fs_builder &bld,
 
    case nir_intrinsic_load_per_vertex_input:
       emit_gs_input_load(dest, instr->src[0], instr->const_index[0],
-                         instr->src[1], instr->num_components);
+                         instr->src[1], instr->num_components,
+                         nir_intrinsic_component(instr));
       break;
 
    case nir_intrinsic_emit_vertex_with_counter:
-- 
2.5.5