[Mesa-dev] [PATCH 18/24] i965: Update assertion to account for Gen < 7

[Ian Romanick]

From: Ian Romanick <ian.d.romanick at intel.com>

Previously SHADER_OPCODE_MULH could only exist on Gen7+, so the
assertion assumed the Gen7+ accumulator rules.  A future patch will
allow this instruction on at least Gen6, so update the assertion.

Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
---
 src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 2f473cc..0a48df9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -43,6 +43,9 @@
 
 using namespace brw;
 
+static unsigned get_fpu_lowered_simd_width(const struct brw_device_info *,
+                                           const fs_inst *);
+
 void
 fs_inst::init(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
               const fs_reg *src, unsigned sources)
@@ -3658,7 +3661,8 @@ fs_visitor::lower_integer_multiplication()
 
       } else if (inst->opcode == SHADER_OPCODE_MULH) {
          /* Should have been lowered to 8-wide. */
-         assert(inst->exec_size <= 8);
+         assert(inst->exec_size <=
+                (devinfo->gen >= 7 ? 8 : get_fpu_lowered_simd_width(devinfo, inst)));
          const fs_reg acc = retype(brw_acc_reg(inst->exec_size),
                                    inst->dst.type);
          fs_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]);
-- 
2.5.5