[Mesa-dev] [PATCH 1/2] nvc0: fix up image support for allowing multiple samples
Samuel Pitoiset
samuel.pitoiset at gmail.com
Wed Jun 29 21:42:28 UTC 2016
On 06/29/2016 06:13 AM, Ilia Mirkin wrote:
> Basically we just have to scale up the coordinates and then add the
> relevant sample offset. The code to handle this was already largely
> present from Christoph's earlier attempts to pipe images through back in
> the dark ages, this just hooks it all up.
>
> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
>
> Only tested on GK208... probably would be good for someone on GF1xx to give it a shot.
Tested on GF119 (ie. piglit-run -t arb_shader_image_load_store ...),
works fine.
>
> .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 3 +++
> .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 4 ++++
> src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 24 ++++++++++++++++++++++
> src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 2 +-
> src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 20 ++++++++----------
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 20 ++++++++++++++++++
> src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 6 ++++--
> 7 files changed, 64 insertions(+), 15 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> index 0fa5aa1..f3d7bee 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -2388,6 +2388,9 @@ Converter::getImageCoords(std::vector<Value *> &coords, int r, int s)
>
> for (int c = 0; c < arg; ++c)
> coords.push_back(fetchSrc(s, c));
> +
> + if (t.isMS())
> + coords.push_back(fetchSrc(s, 3));
> }
>
> // For raw loads, granularity is 4 byte.
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> index 67bd73b..73b680a 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> @@ -2044,6 +2044,10 @@ NVC0LoweringPass::processSurfaceCoordsNVC0(TexInstruction *su)
> Value *v;
> Value *ind = NULL;
>
> + bld.setPosition(su, false);
> +
> + adjustCoordinatesMS(su);
> +
> if (su->tex.rIndirectSrc >= 0) {
> ind = su->getIndirectR();
> if (su->tex.r > 0) {
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
> index 7511819..f5f7fd4 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
> @@ -113,6 +113,30 @@ nvc0_screen_compute_setup(struct nvc0_screen *screen,
> PUSH_DATA (push, screen->txc->offset + 65536);
> PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
>
> + /* MS sample coordinate offsets */
> + BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
> + PUSH_DATA (push, 2048);
> + PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
> + PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5));
> + BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + 2 * 8);
> + PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
> + PUSH_DATA (push, 0); /* 0 */
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, 1); /* 1 */
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, 0); /* 2 */
> + PUSH_DATA (push, 1);
> + PUSH_DATA (push, 1); /* 3 */
> + PUSH_DATA (push, 1);
> + PUSH_DATA (push, 2); /* 4 */
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, 3); /* 5 */
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, 2); /* 6 */
> + PUSH_DATA (push, 1);
> + PUSH_DATA (push, 3); /* 7 */
> + PUSH_DATA (push, 1);
> +
> return 0;
> }
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
> index 8a965fc..c633ccf 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
> @@ -112,7 +112,7 @@
> #define NVC0_CB_AUX_TEX_INFO(i) 0x020 + (i) * 4
> #define NVC0_CB_AUX_TEX_SIZE (32 * 4)
> /* 8 sets of 32-bits coordinate offsets */
> -#define NVC0_CB_AUX_MS_INFO 0x0a0 /* CP */
> +#define NVC0_CB_AUX_MS_INFO 0x0a0
> #define NVC0_CB_AUX_MS_SIZE (8 * 2 * 4)
> /* block/grid size, at 3 32-bits integers each and gridid */
> #define NVC0_CB_AUX_GRID_INFO 0x0e0 /* CP */
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> index aba9511..d75b702 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> @@ -555,29 +555,25 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
>
> info->io.genUserClip = prog->vp.num_ucps;
> info->io.auxCBSlot = 15;
> + info->io.msInfoCBSlot = 15;
> info->io.ucpBase = NVC0_CB_AUX_UCP_INFO;
> info->io.drawInfoBase = NVC0_CB_AUX_DRAW_INFO;
> + info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
> + info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
> + info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
> + if (chipset >= NVISA_GK104_CHIPSET) {
> + info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
> + }
>
> if (prog->type == PIPE_SHADER_COMPUTE) {
> if (chipset >= NVISA_GK104_CHIPSET) {
> info->io.auxCBSlot = 7;
> - info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
> + info->io.msInfoCBSlot = 7;
> info->prop.cp.gridInfoBase = NVC0_CB_AUX_GRID_INFO;
> info->io.uboInfoBase = NVC0_CB_AUX_UBO_INFO(0);
> }
> - info->io.msInfoCBSlot = 0;
> - info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
> - info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
> - info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
> } else {
> - if (chipset >= NVISA_GK104_CHIPSET) {
> - info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
> - }
> info->io.sampleInfoBase = NVC0_CB_AUX_SAMPLE_INFO;
> - info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
> - info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
> - info->io.msInfoCBSlot = 15;
> - info->io.msInfoBase = 0; /* TODO */
> }
>
> info->assignSlots = nvc0_program_assign_varying_slots;
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index ce6bd8b..2a36d42 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -977,6 +977,26 @@ nvc0_screen_create(struct nouveau_device *dev)
> BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
> PUSH_DATA (push, 0x54);
> }
> +
> + /* MS sample coordinate offsets: these do not work with _ALT modes ! */
> + BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
> + PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
> + PUSH_DATA (push, 0); /* 0 */
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, 1); /* 1 */
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, 0); /* 2 */
> + PUSH_DATA (push, 1);
> + PUSH_DATA (push, 1); /* 3 */
> + PUSH_DATA (push, 1);
> + PUSH_DATA (push, 2); /* 4 */
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, 3); /* 5 */
> + PUSH_DATA (push, 0);
> + PUSH_DATA (push, 2); /* 6 */
> + PUSH_DATA (push, 1);
> + PUSH_DATA (push, 3); /* 7 */
> + PUSH_DATA (push, 1);
> }
> BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
> PUSH_DATA (push, 0);
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
> index baf39aa..fc934b3 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
> @@ -774,9 +774,11 @@ nvc0_get_surface_dims(struct pipe_image_view *view, int *width, int *height,
> return;
> }
>
> + struct nv50_miptree *mt = nv50_miptree(view->resource);
> +
> level = view->u.tex.level;
> - *width = u_minify(view->resource->width0, level);
> - *height = u_minify(view->resource->height0, level);
> + *width = u_minify(view->resource->width0, level) << mt->ms_x;
> + *height = u_minify(view->resource->height0, level) << mt->ms_y;
> *depth = u_minify(view->resource->depth0, level);
>
> switch (res->base.target) {
>
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