[Mesa-dev] [PATCH 08/36] i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled
Pohjolainen, Topi
topi.pohjolainen at intel.com
Thu Jun 30 05:57:29 UTC 2016
On Wed, Jun 29, 2016 at 05:37:27PM -0700, Jason Ekstrand wrote:
> Now that we're carrying around the isl_surf, we can just modify it
> directly instead of passing an extra bit around.
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 14 ++--------
> src/mesa/drivers/dri/i965/brw_blorp.h | 15 -----------
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 40 ++++++++++++++++++----------
> 3 files changed, 28 insertions(+), 41 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 353cc78..0e8eb1f 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -71,7 +71,6 @@ brw_blorp_surface_info_init(struct brw_context *brw,
>
> info->num_samples = mt->num_samples;
> info->array_layout = mt->array_layout;
> - info->map_stencil_as_y_tiled = false;
> info->msaa_layout = mt->msaa_layout;
> info->swizzle = SWIZZLE_XYZW;
>
> @@ -80,11 +79,8 @@ brw_blorp_surface_info_init(struct brw_context *brw,
>
> switch (format) {
> case MESA_FORMAT_S_UINT8:
> - /* The miptree is a W-tiled stencil buffer. Surface states can't be set
> - * up for W tiling, so we'll need to use Y tiling and have the WM
> - * program swizzle the coordinates.
> - */
> - info->map_stencil_as_y_tiled = true;
> + assert(info->surf.tiling == ISL_TILING_W);
> + /* Prior to Broadwell, we can't render to R8_UINT */
Thanks for adding the comment and the assert.
Patches seven and eight are:
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> info->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
> BRW_SURFACEFORMAT_R8_UNORM;
> break;
> @@ -299,12 +295,6 @@ brw_blorp_emit_surface_state(struct brw_context *brw,
> surf.image_alignment_el = isl_extent3d(4, 2, 1);
> }
>
> - if (surface->map_stencil_as_y_tiled) {
> - /* We need to fake W-tiling with Y-tiling */
> - surf.tiling = ISL_TILING_Y0;
> - surf.row_pitch *= 2;
> - }
> -
> union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
>
> const struct isl_surf *aux_surf = NULL;
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
> index 7611a8f..2387315 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.h
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.h
> @@ -118,21 +118,6 @@ struct brw_blorp_surface_info
> */
> uint32_t y_offset;
>
> - /* Setting this flag indicates that the buffer's contents are W-tiled
> - * stencil data, but the surface state should be set up for Y tiled
> - * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
> - * support W tiling).
> - *
> - * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
> - * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
> - * pitch stored in the surface state will be multiplied by 2, and the
> - * height will be halved. Also, since W and Y tiles store their data in a
> - * different order, the width and height will be rounded up to a multiple
> - * of the tile size, to ensure that the WM program can access the full
> - * width and height of the buffer.
> - */
> - bool map_stencil_as_y_tiled;
> -
> unsigned num_samples;
>
> /**
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> index cdb6b33..1e15bd5 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> @@ -1734,16 +1734,6 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> params.dst.num_samples = 0;
> }
>
> - if (params.dst.map_stencil_as_y_tiled && params.dst.num_samples > 1) {
> - /* If the destination surface is a W-tiled multisampled stencil buffer
> - * that we're mapping as Y tiled, then we need to arrange for the WM
> - * program to run once per sample rather than once per pixel, because
> - * the memory layout of related samples doesn't match between W and Y
> - * tiling.
> - */
> - wm_prog_key.persample_msaa_dispatch = true;
> - }
> -
> if (params.src.num_samples > 0 && params.dst.num_samples > 1) {
> /* We are blitting from a multisample buffer to a multisample buffer, so
> * we must preserve samples within a pixel. This means we have to
> @@ -1827,8 +1817,6 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS)
> wm_prog_key.dst_layout = INTEL_MSAA_LAYOUT_NONE;
>
> - wm_prog_key.src_tiled_w = params.src.map_stencil_as_y_tiled;
> - wm_prog_key.dst_tiled_w = params.dst.map_stencil_as_y_tiled;
> /* Round floating point values to nearest integer to avoid "off by one texel"
> * kind of errors when blitting.
> */
> @@ -1901,7 +1889,23 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> wm_prog_key.use_kill = true;
> }
>
> - if (params.dst.map_stencil_as_y_tiled) {
> + if (params.dst.surf.tiling == ISL_TILING_W) {
> + /* We need to fake W-tiling with Y-tiling */
> + params.dst.surf.tiling = ISL_TILING_Y0;
> + params.dst.surf.row_pitch *= 2;
> +
> + wm_prog_key.dst_tiled_w = true;
> +
> + if (params.dst.num_samples > 1) {
> + /* If the destination surface is a W-tiled multisampled stencil
> + * buffer that we're mapping as Y tiled, then we need to arrange for
> + * the WM program to run once per sample rather than once per pixel,
> + * because the memory layout of related samples doesn't match between
> + * W and Y tiling.
> + */
> + wm_prog_key.persample_msaa_dispatch = true;
> + }
> +
> /* We must modify the rectangle we send through the rendering pipeline
> * (and the size and x/y offset of the destination surface), to account
> * for the fact that we are mapping it as Y-tiled when it is in fact
> @@ -1960,7 +1964,15 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> wm_prog_key.use_kill = true;
> }
>
> - if (params.src.map_stencil_as_y_tiled) {
> + if (brw->gen < 8 && params.src.surf.tiling == ISL_TILING_W) {
> + /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
> + * Broadwell adds support for sampling from stencil.
> + */
> + params.src.surf.tiling = ISL_TILING_Y0;
> + params.src.surf.row_pitch *= 2;
> +
> + wm_prog_key.src_tiled_w = true;
> +
> /* We must modify the size and x/y offset of the source surface to
> * account for the fact that we are mapping it as Y-tiled when it is in
> * fact W tiled.
> --
> 2.5.0.400.gff86faf
>
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