[Mesa-dev] [PATCH 1/2] radeon/vce: check alignment for dpb buffer

[Leo Liu]

On 06/30/2016 03:19 AM, Christian König wrote:
> Am 29.06.2016 um 21:53 schrieb Leo Liu:
>> This will make safer for not acrossing the boundary
>>
>> Signed-off-by: Leo Liu <leo.liu at amd.com>
>> ---
>>   src/gallium/drivers/radeon/radeon_vce.c | 8 +++++++-
>>   1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/radeon/radeon_vce.c 
>> b/src/gallium/drivers/radeon/radeon_vce.c
>> index e8aac8e..0a41311 100644
>> --- a/src/gallium/drivers/radeon/radeon_vce.c
>> +++ b/src/gallium/drivers/radeon/radeon_vce.c
>> @@ -52,6 +52,8 @@
>>   #define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
>>   #define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8))
>>   +#define RVCE_CPB_BUFFER_ALIGNMENT (16 * 16 * 2 * 1024 * 1024)
>
> 512MB alignment? Well that sounds like way to much.

Oops, that's too big. Back to the drawing board double check.

Thanks,
Leo

>
> Usually even for the worst tiling modes you don't need more than 2MB.
>
> Regards,
> Christian.
>
>> +
>>   /**
>>    * flush commands to the hardware
>>    */
>> @@ -461,7 +463,11 @@ struct pipe_video_codec 
>> *rvce_create_encoder(struct pipe_context *context,
>>           cpb_size +=  RVCE_MAX_AUX_BUFFER_NUM *
>>               RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
>>       tmp_buf->destroy(tmp_buf);
>> -    if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, 
>> PIPE_USAGE_DEFAULT)) {
>> +    enc->cpb.usage = PIPE_USAGE_DEFAULT;
>> +    enc->cpb.res = (struct r600_resource 
>> *)r600_aligned_buffer_create(enc->screen,
>> +                    PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
>> +                    cpb_size, RVCE_CPB_BUFFER_ALIGNMENT);
>> +    if (!enc->cpb.res) {
>>           RVID_ERR("Can't create CPB buffer.\n");
>>           goto error;
>>       }
>