[Mesa-dev] [PATCH] radeonsi: fix texture border colors for compute shaders
Edward O'Callaghan
funfunctor at folklore1984.net
Wed Oct 5 00:40:43 UTC 2016
Acked-by: Edward O'Callaghan <funfunctor at folklore1984.net>
On 10/05/2016 10:51 AM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> There are VM faults without this.
>
> Cc: 12.0 <mesa-stable at lists.freedesktop.org>
> ---
> src/gallium/drivers/radeonsi/si_compute.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
> index 9a5a4a9..1d1df2f 100644
> --- a/src/gallium/drivers/radeonsi/si_compute.c
> +++ b/src/gallium/drivers/radeonsi/si_compute.c
> @@ -201,20 +201,21 @@ static void si_set_global_binding(
> offset = util_le32_to_cpu(*handles[i]);
> va += offset;
> va = util_cpu_to_le64(va);
> memcpy(handles[i], &va, sizeof(va));
> }
> }
>
> static void si_initialize_compute(struct si_context *sctx)
> {
> struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
> + uint64_t bc_va;
>
> radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
> radeon_emit(cs, 0);
> radeon_emit(cs, 0);
> radeon_emit(cs, 0);
>
> radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
> /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
> radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
> radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
> @@ -235,20 +236,31 @@ static void si_initialize_compute(struct si_context *sctx)
> * which is now 0x22f.
> */
> if (sctx->b.chip_class <= SI) {
> /* XXX: This should be:
> * (number of compute units) * 4 * (waves per simd) - 1 */
>
> radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID,
> 0x190 /* Default value */);
> }
>
> + /* Set the pointer to border colors. */
> + bc_va = sctx->border_color_buffer->gpu_address;
> +
> + if (sctx->b.chip_class >= CIK) {
> + radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
> + radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
> + radeon_emit(cs, bc_va >> 40); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
> + } else {
> + radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
> + }
> +
> sctx->cs_shader_state.emitted_program = NULL;
> sctx->cs_shader_state.initialized = true;
> }
>
> static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
> struct si_shader *shader,
> struct si_shader_config *config)
> {
> uint64_t scratch_bo_size, scratch_needed;
> scratch_bo_size = 0;
>
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