[Mesa-dev] [PATCH 06/13] st/glsl_to_tgsi: explicit handling of writemask for depth/stencil export

Nicolai Hähnle nhaehnle at gmail.com
Fri Oct 7 19:55:17 UTC 2016


From: Nicolai Hähnle <nicolai.haehnle at amd.com>

---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index bb88196..3c2870d 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -2861,33 +2861,42 @@ glsl_to_tgsi_visitor::visit(ir_assignment *ir)
             case 3:
                l.writemask = WRITEMASK_XYZ;
                break;
             case 4:
                l.writemask = WRITEMASK_XYZW;
                break;
             }
          } else
             l.writemask = WRITEMASK_XYZW;
       }
-   } else if (ir->lhs->type->is_scalar() &&
-              !ir->lhs->type->is_64bit() &&
-              ir->lhs->variable_referenced()->data.mode == ir_var_shader_out) {
-      /* FINISHME: This hack makes writing to gl_FragDepth, which lives in the
-       * FINISHME: W component of fragment shader output zero, work correctly.
-       */
-      l.writemask = WRITEMASK_XYZW;
    } else {
       int swizzles[4];
       int first_enabled_chan = 0;
       int rhs_chan = 0;
+      ir_variable *variable = ir->lhs->variable_referenced();
+
+      if (shader->Stage == MESA_SHADER_FRAGMENT &&
+          variable->data.mode == ir_var_shader_out &&
+          (variable->data.location == FRAG_RESULT_DEPTH ||
+           variable->data.location == FRAG_RESULT_STENCIL)) {
+         assert(ir->lhs->type->is_scalar());
+         assert(ir->write_mask == WRITEMASK_X);
 
-      l.writemask = ir->write_mask;
+         if (variable->data.location == FRAG_RESULT_DEPTH)
+            l.writemask = WRITEMASK_Z;
+         else {
+            assert(variable->data.location == FRAG_RESULT_STENCIL);
+            l.writemask = WRITEMASK_Y;
+         }
+      } else {
+         l.writemask = ir->write_mask;
+      }
 
       for (int i = 0; i < 4; i++) {
          if (l.writemask & (1 << i)) {
             first_enabled_chan = GET_SWZ(r.swizzle, i);
             break;
          }
       }
 
       /* Swizzle a small RHS vector into the channels being written.
        *
-- 
2.7.4



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