[Mesa-dev] [PATCH 07/13] st/glsl_to_tgsi: simpler fixup of empty writemasks

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

Empty writemasks mean "copy everything", so we can always just use the number
of vector elements (which uses the GLSL meaning here, i.e. each double is a
single element/writemask bit).
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 37 ++++++++----------------------
 1 file changed, 10 insertions(+), 27 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 3c2870d..444f5f7 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -2835,65 +2835,48 @@ void
 glsl_to_tgsi_visitor::visit(ir_assignment *ir)
 {
    st_dst_reg l;
    st_src_reg r;
 
    ir->rhs->accept(this);
    r = this->result;
 
    l = get_assignment_lhs(ir->lhs, this);
 
-   /* FINISHME: This should really set to the correct maximal writemask for each
-    * FINISHME: component written (in the loops below).  This case can only
-    * FINISHME: occur for matrices, arrays, and structures.
-    */
-   if (ir->write_mask == 0) {
-      assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
-
-      if (ir->lhs->type->is_array() || ir->lhs->type->without_array()->is_matrix()) {
-         if (ir->lhs->type->without_array()->is_64bit()) {
-            switch (ir->lhs->type->without_array()->vector_elements) {
-            case 1:
-               l.writemask = WRITEMASK_X;
-               break;
-            case 2:
-               l.writemask = WRITEMASK_XY;
-               break;
-            case 3:
-               l.writemask = WRITEMASK_XYZ;
-               break;
-            case 4:
-               l.writemask = WRITEMASK_XYZW;
-               break;
-            }
-         } else
-            l.writemask = WRITEMASK_XYZW;
-      }
-   } else {
+   {
       int swizzles[4];
       int first_enabled_chan = 0;
       int rhs_chan = 0;
       ir_variable *variable = ir->lhs->variable_referenced();
 
       if (shader->Stage == MESA_SHADER_FRAGMENT &&
           variable->data.mode == ir_var_shader_out &&
           (variable->data.location == FRAG_RESULT_DEPTH ||
            variable->data.location == FRAG_RESULT_STENCIL)) {
          assert(ir->lhs->type->is_scalar());
          assert(ir->write_mask == WRITEMASK_X);
 
          if (variable->data.location == FRAG_RESULT_DEPTH)
             l.writemask = WRITEMASK_Z;
          else {
             assert(variable->data.location == FRAG_RESULT_STENCIL);
             l.writemask = WRITEMASK_Y;
          }
+      } else if (ir->write_mask == 0) {
+         assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
+
+         if (ir->lhs->type->is_array() || ir->lhs->type->is_matrix()) {
+            unsigned num_elements = ir->lhs->type->without_array()->vector_elements;
+            l.writemask = u_bit_consecutive(0, num_elements);
+         } else {
+            l.writemask = WRITEMASK_XYZW;
+         }
       } else {
          l.writemask = ir->write_mask;
       }
 
       for (int i = 0; i < 4; i++) {
          if (l.writemask & (1 << i)) {
             first_enabled_chan = GET_SWZ(r.swizzle, i);
             break;
          }
       }
-- 
2.7.4