[Mesa-dev] [PATCH v2 6/6] nv50/ra: always prefer def == src2 for mad/sad

Karol Herbst karolherbst at gmail.com
Sun Oct 9 09:04:56 UTC 2016


improves the post ra mad folding pass:
total instructions in shared programs : 2811662 -> 2808429 (-0.11%)
total gprs used in shared programs    : 379273 -> 379236 (-0.01%)
total local used in shared programs   : 9505 -> 9505 (0.00%)
total bytes used in shared programs   : 25773432 -> 25743616 (-0.12%)

                local        gpr       inst      bytes
    helped           0          26        1736        1736
      hurt           0          20          78          78

v2: reorder to show the benefit of this patch

Signed-off-by: Karol Herbst <karolherbst at gmail.com>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 7e64f7c..0cf35b7 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -1468,8 +1468,7 @@ GCRA::allocateRegisters(ArrayList& insns)
          nodes[i].init(regs, lval);
          RIG.insert(&nodes[i]);
 
-         if (lval->inFile(FILE_GPR) && lval->getInsn() != NULL &&
-             prog->getTarget()->getChipset() < 0xc0) {
+         if (lval->inFile(FILE_GPR) && lval->getInsn() != NULL) {
             Instruction *insn = lval->getInsn();
             if (insn->op == OP_MAD || insn->op == OP_SAD)
                // Short encoding only possible if they're all GPRs, no need to
-- 
2.10.0



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