[Mesa-dev] [PATCH 3/5] anv/cmd_buffer: Rename full_surface_op to full_surf_clear

[Nanley Chery]

This matches the HW docs and specifies what the variable is actually
concerned with.

Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
---
 src/intel/vulkan/gen8_cmd_buffer.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c
index e88ab02..97a035b 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -422,7 +422,7 @@ genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
 
    struct anv_cmd_state *cmd_state = &cmd_buffer->state;
    const uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
-   bool full_surface_op;
+   bool full_surf_clear;
 
    /* This variable corresponds to the Pixel Dim column in the table below */
    struct isl_extent2d px_dim;
@@ -441,14 +441,13 @@ genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
        * Therefore, the only way the extent of the render area can match that of
        * the image view is if the render area offset equals (0, 0).
        */
-      full_surface_op =
+      full_surf_clear =
              cmd_state->render_area.extent.width == iview->extent.width &&
              cmd_state->render_area.extent.height == iview->extent.height;
-      if (full_surface_op)
+      if (full_surf_clear)
          assert(cmd_state->render_area.offset.x == 0 &&
                 cmd_state->render_area.offset.y == 0);
 
-
       /* Apply alignment restrictions. Despite the BDW PRM mentioning this is
        * only needed for a depth buffer surface type of D16_UNORM, testing
        * showed it to be necessary for other depth formats as well
@@ -485,7 +484,7 @@ genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
       px_dim = (struct isl_extent2d) { .w = 8, .h = 4};
 #endif
 
-      if (!full_surface_op) {
+      if (!full_surf_clear) {
          /* Fast depth clears clear an entire sample block at a time. As a
           * result, the rectangle must be aligned to the pixel dimensions of
           * a sample block for a successful operation.
@@ -531,7 +530,7 @@ genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
                             cmd_state->attachments[ds].pending_clear_aspects;
          hzp.DepthBufferClearEnable = VK_IMAGE_ASPECT_DEPTH_BIT &
                             cmd_state->attachments[ds].pending_clear_aspects;
-         hzp.FullSurfaceDepthandStencilClear = full_surface_op;
+         hzp.FullSurfaceDepthandStencilClear = full_surf_clear;
          hzp.StencilClearValue =
             cmd_state->attachments[ds].clear_value.depthStencil.stencil & 0xff;
 
@@ -585,7 +584,7 @@ genX(cmd_buffer_emit_hz_op)(struct anv_cmd_buffer *cmd_buffer,
 
    anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_WM_HZ_OP), hzp);
 
-   if (!full_surface_op && op == BLORP_HIZ_OP_DEPTH_CLEAR) {
+   if (!full_surf_clear && op == BLORP_HIZ_OP_DEPTH_CLEAR) {
       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
          pc.DepthStallEnable = true;
          pc.DepthCacheFlushEnable = true;
-- 
2.10.0