[Mesa-dev] [PATCH v2 007/103] i965/vec4/nir: fix emitting 64-bit immediates

Ian Romanick idr at freedesktop.org
Wed Oct 19 00:20:11 UTC 2016


On 10/11/2016 02:01 AM, Iago Toral Quiroga wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 22 ++++++++++++++++++----
>  1 file changed, 18 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 05e7f29..ce95c8d 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -352,8 +352,15 @@ vec4_visitor::get_indirect_offset(nir_intrinsic_instr *instr)
>  void
>  vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
>  {
> -   dst_reg reg = dst_reg(VGRF, alloc.allocate(1));
> -   reg.type =  BRW_REGISTER_TYPE_D;
> +   dst_reg reg;
> +
> +   if (instr->def.bit_size == 64) {
> +      reg = dst_reg(VGRF, alloc.allocate(2));
> +      reg.type = BRW_REGISTER_TYPE_DF;

For 32-bits we use an integer type (D).  Should was also use an integer
type (Q) here?  I'm worried that I'll have problems with this when I add
int64 support.

> +   } else {
> +      reg = dst_reg(VGRF, alloc.allocate(1));
> +      reg.type = BRW_REGISTER_TYPE_D;
> +   }
>  
>     unsigned remaining = brw_writemask_for_size(instr->def.num_components);
>  
> @@ -368,13 +375,20 @@ vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
>           continue;
>  
>        for (unsigned j = i; j < instr->def.num_components; j++) {
> -         if (instr->value.u32[i] == instr->value.u32[j]) {
> +         if ((instr->def.bit_size == 32 &&
> +              instr->value.u32[i] == instr->value.u32[j]) ||
> +             (instr->def.bit_size == 64 &&
> +              instr->value.f64[i] == instr->value.f64[j])) {
>              writemask |= 1 << j;
>           }
>        }
>  
>        reg.writemask = writemask;
> -      emit(MOV(reg, brw_imm_d(instr->value.i32[i])));
> +      if (instr->def.bit_size == 64) {
> +         emit(MOV(reg, brw_imm_df(instr->value.f64[i])));
> +      } else {
> +         emit(MOV(reg, brw_imm_d(instr->value.i32[i])));
> +      }
>  
>        remaining &= ~writemask;
>     }
> 



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