[Mesa-dev] [PATCH v2 007/103] i965/vec4/nir: fix emitting 64-bit immediates

[Matt Turner]

On Tue, Oct 18, 2016 at 5:20 PM, Ian Romanick <idr at freedesktop.org> wrote:
> On 10/11/2016 02:01 AM, Iago Toral Quiroga wrote:
>> ---
>>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 22 ++++++++++++++++++----
>>  1 file changed, 18 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>> index 05e7f29..ce95c8d 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
>> @@ -352,8 +352,15 @@ vec4_visitor::get_indirect_offset(nir_intrinsic_instr *instr)
>>  void
>>  vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
>>  {
>> -   dst_reg reg = dst_reg(VGRF, alloc.allocate(1));
>> -   reg.type =  BRW_REGISTER_TYPE_D;
>> +   dst_reg reg;
>> +
>> +   if (instr->def.bit_size == 64) {
>> +      reg = dst_reg(VGRF, alloc.allocate(2));
>> +      reg.type = BRW_REGISTER_TYPE_DF;
>
> For 32-bits we use an integer type (D).  Should was also use an integer
> type (Q) here?  I'm worried that I'll have problems with this when I add
> int64 support.

Q only exists on Broadwell and newer, so I don't think it's usable
here (at least for HSW/IVB).