[Mesa-dev] [PATCH v2 004/103] i965/vec4/nir: Add bit-size information to types

[Iago Toral]

On Tue, 2016-10-18 at 17:16 -0700, Ian Romanick wrote:
> On 10/11/2016 02:01 AM, Iago Toral Quiroga wrote:
> > 
> > Reviewed-by: Francisco Jerez <currojerez at riseup.net>
> > ---
> >  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> > b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> > index af76730..5048c4e 100644
> > --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> > @@ -325,7 +325,7 @@ src_reg
> >  vec4_visitor::get_nir_src(const nir_src &src, unsigned
> > num_components)
> >  {
> >     /* if type is not specified, default to signed int */
> > -   return get_nir_src(src, nir_type_int, num_components);
> > +   return get_nir_src(src, nir_type_int32, num_components);
> >  }
> >  
> >  src_reg
> > @@ -747,7 +747,7 @@
> > vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
> >        const nir_intrinsic_info *info = &nir_intrinsic_infos[instr-
> > >intrinsic];
> >  
> >        /* Get the arguments of the atomic intrinsic. */
> > -      src_reg offset = get_nir_src(instr->src[0], nir_type_int,
> > +      src_reg offset = get_nir_src(instr->src[0], nir_type_int32,
> >                                     instr->num_components);
> >        const src_reg surface = brw_imm_ud(surf_index);
> >        const src_reg src0 = (info->num_srcs >= 2
> > @@ -793,7 +793,7 @@
> > vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
> >            * from any live channel.
> >            */
> >           surf_index = src_reg(this, glsl_type::uint_type);
> > -         emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[0],
> > nir_type_int,
> > +         emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[0],
> > nir_type_int32,
> >                                                     instr-
> > >num_components),
> >                    brw_imm_ud(prog_data-
> > >base.binding_table.ubo_start)));
> >           surf_index = emit_uniformize(surf_index);
> > @@ -811,7 +811,7 @@
> > vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
> >        if (const_offset) {
> >           offset = brw_imm_ud(const_offset->u32[0] & ~15);
> >        } else {
> > -         offset = get_nir_src(instr->src[1], nir_type_int, 1);
> > +         offset = get_nir_src(instr->src[1], nir_type_uint32, 1);
> Does it matter that this changed form int to uint32?

At some point in the past we made brw_type_for_nir_type() only accept
bit-sized alu types, so this patch was necessary for things to work.
That's not the case now so this patch should not be necessary anymore
(a quick run of the fp64 tests shows no regressions without this
patch). I guess it does not hurt to add the bit-size information when
it is known though, but I think it is safe to drop this if you think it
is not worth it.

Iago

> > 
> >        }
> >  
> >        src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
> > 
>