[Mesa-dev] [PATCH 3/4] winsys/amdgpu: fix radeon_surf::macro_tile_index for imported textures

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

Maybe this is why SDMA has been broken for many amdgpu users?

SDMA is the only block which is used with imported textures and relies
on this variable. DB also uses it, but it doesn't get imported textures,
so it's unaffected.

I do get SDMA failures on Tonga before this patch if R600_DEBUG=testdma
is changed to use imported textures.

Cc: 11.2 12.0 13.0 <mesa-stable at lists.freedesktop.org>
---
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 1bf07a7..c5462bc 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -296,20 +296,34 @@ static void set_micro_tile_mode(struct radeon_surf *surf,
                                 struct radeon_info *info)
 {
    uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
 
    if (info->chip_class >= CIK)
       surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
    else
       surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 }
 
+static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
+{
+	unsigned index, tileb;
+
+	tileb = 8 * 8 * surf->bpe;
+	tileb = MIN2(surf->tile_split, tileb);
+
+	for (index = 0; tileb > 64; index++)
+		tileb >>= 1;
+
+	assert(index < 16);
+	return index;
+}
+
 static int amdgpu_surface_init(struct radeon_winsys *rws,
                                struct radeon_surf *surf)
 {
    struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
    unsigned level, mode, type;
    bool compressed;
    ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
    ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
    ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
    ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
@@ -468,20 +482,23 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
                AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
             else
                AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
          }
       } else {
          /* CIK - VI */
          if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
             AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
          else
             AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
+
+         /* Addrlib doesn't set this if tileIndex is forced like above. */
+         AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
       }
    }
 
    surf->bo_size = 0;
    surf->dcc_size = 0;
    surf->dcc_alignment = 1;
    surf->htile_size = 0;
    surf->htile_alignment = 1;
 
    /* Calculate texture layout information. */
-- 
2.7.4