[Mesa-dev] [PATCH 20/24] gallium/radeon: don't force the same tiling parameters for FMASK

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

GCN can use a completely different tile mode for FMASK.

FMASK allocation now skips one unrelated amdgpu_surface_init codepath as
hinted by the assertion.
---
 src/gallium/drivers/radeon/r600_texture.c      | 18 ++++++++++--------
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c |  2 ++
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 2f2c17c..f79eae2 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -586,33 +586,35 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
 	/* FMASK is allocated like an ordinary texture. */
 	struct pipe_resource templ = rtex->resource.b.b;
 	struct radeon_surf fmask = {};
 	unsigned flags, bpe;
 
 	memset(out, 0, sizeof(*out));
 
 	templ.nr_samples = 1;
 	flags = rtex->surface.flags | RADEON_SURF_FMASK;
 
-	/* Use the same parameters and tile mode. */
-	fmask.bankw = rtex->surface.bankw;
-	fmask.bankh = rtex->surface.bankh;
-	fmask.mtilea = rtex->surface.mtilea;
-	fmask.tile_split = rtex->surface.tile_split;
+	if (rscreen->chip_class <= CAYMAN) {
+		/* Use the same parameters and tile mode. */
+		fmask.bankw = rtex->surface.bankw;
+		fmask.bankh = rtex->surface.bankh;
+		fmask.mtilea = rtex->surface.mtilea;
+		fmask.tile_split = rtex->surface.tile_split;
+
+		if (nr_samples <= 4)
+			fmask.bankh = 4;
+	}
 
 	switch (nr_samples) {
 	case 2:
 	case 4:
 		bpe = 1;
-		if (rscreen->chip_class <= CAYMAN) {
-			fmask.bankh = 4;
-		}
 		break;
 	case 8:
 		bpe = 4;
 		break;
 	default:
 		R600_ERR("Invalid sample count for FMASK allocation.\n");
 		return;
 	}
 
 	/* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index ff71bcb..45edcc2 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -429,20 +429,22 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
     * TODO: update addrlib to a newer version, remove this, and
     * use flags.matchStencilTileCfg = 1 as an alternative fix.
     */
   if (tex->last_level > 0)
       AddrSurfInfoIn.flags.noStencil = 1;
 
    /* Set preferred macrotile parameters. This is usually required
     * for shared resources. This is for 2D tiling only. */
    if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
        surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
+      assert(!(flags & RADEON_SURF_FMASK));
+
       /* If any of these parameters are incorrect, the calculation
        * will fail. */
       AddrTileInfoIn.banks = surf->num_banks;
       AddrTileInfoIn.bankWidth = surf->bankw;
       AddrTileInfoIn.bankHeight = surf->bankh;
       AddrTileInfoIn.macroAspectRatio = surf->mtilea;
       AddrTileInfoIn.tileSplitBytes = surf->tile_split;
       AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
       AddrSurfInfoIn.flags.degrade4Space = 0;
       AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
-- 
2.7.4