[Mesa-dev] [PATCH 1/3] nvc0: more use of nve4_p2mf_push_linear() in compute path
Samuel Pitoiset
samuel.pitoiset at gmail.com
Wed Oct 26 20:00:09 UTC 2016
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 72 ++++++-------------------
1 file changed, 16 insertions(+), 56 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
index d661c00..2c6de86 100644
--- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
@@ -193,10 +193,7 @@ gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
{
struct nv04_resource *res = nv04_resource(view->resource);
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
- struct nvc0_screen *screen = nvc0->screen;
- struct nouveau_bo *txc = nvc0->screen->txc;
struct nv50_tic_entry *tic;
- uint64_t address;
const int s = 5;
tic = nv50_tic_entry(nvc0->images_tic[s][slot]);
@@ -208,16 +205,8 @@ gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
/* upload the texture view */
- PUSH_SPACE(push, 16);
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, txc->offset + (tic->id * 32));
- PUSH_DATA (push, txc->offset + (tic->id * 32));
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
- PUSH_DATA (push, 32);
- PUSH_DATA (push, 1);
- BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
- PUSH_DATAp(push, &tic->tic[0], 8);
+ nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32,
+ NV_VRAM_DOMAIN(&nvc0->screen->base), 32, tic->tic);
BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), 1);
PUSH_DATA (push, (tic->id << 4) | 1);
@@ -233,18 +222,10 @@ gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
- address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
-
/* upload the texture handle */
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
- PUSH_DATA (push, address + NVC0_CB_AUX_TEX_INFO(slot + 32));
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
- PUSH_DATA (push, 4);
- PUSH_DATA (push, 0x1);
- BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 2);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
- PUSH_DATA (push, tic->id);
+ nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->uniform_bo,
+ NVC0_CB_AUX_INFO(s) + NVC0_CB_AUX_TEX_INFO(slot + 32),
+ NV_VRAM_DOMAIN(&nvc0->screen->base), 4, &tic->id);
BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
@@ -365,21 +346,14 @@ nve4_compute_validate_constbufs(struct nvc0_context *nvc0)
nvc0->constbuf_dirty[s] &= ~(1 << i);
if (nvc0->constbuf[s][i].user) {
- struct nouveau_bo *bo = nvc0->screen->uniform_bo;
- const unsigned base = NVC0_CB_USR_INFO(s);
- const unsigned size = nvc0->constbuf[s][0].size;
assert(i == 0); /* we really only want OpenGL uniforms here */
assert(nvc0->constbuf[s][0].u.data);
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, bo->offset + base);
- PUSH_DATA (push, bo->offset + base);
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
- PUSH_DATA (push, size);
- PUSH_DATA (push, 0x1);
- BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (size / 4));
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
- PUSH_DATAp(push, nvc0->constbuf[s][0].u.data, size / 4);
+ nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->uniform_bo,
+ NVC0_CB_USR_INFO(s),
+ NV_VRAM_DOMAIN(&nvc0->screen->base),
+ nvc0->constbuf[s][0].size,
+ nvc0->constbuf[s][0].u.data);
}
else {
struct nv04_resource *res =
@@ -494,15 +468,9 @@ nve4_compute_upload_input(struct nvc0_context *nvc0,
address = screen->uniform_bo->offset + NVC0_CB_AUX_INFO(5);
if (cp->parm_size) {
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
- PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_USR_INFO(5));
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
- PUSH_DATA (push, cp->parm_size);
- PUSH_DATA (push, 0x1);
- BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
- PUSH_DATAp(push, info->input, cp->parm_size / 4);
+ nve4_p2mf_push_linear(&nvc0->base, screen->uniform_bo,
+ NVC0_CB_USR_INFO(5), NV_VRAM_DOMAIN(&screen->base),
+ cp->parm_size, info->input);
}
BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
PUSH_DATAh(push, address + NVC0_CB_AUX_GRID_INFO(0));
@@ -698,7 +666,6 @@ out:
static void
nve4_compute_validate_textures(struct nvc0_context *nvc0)
{
- struct nouveau_bo *txc = nvc0->screen->txc;
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
const unsigned s = 5;
unsigned i;
@@ -720,16 +687,9 @@ nve4_compute_validate_textures(struct nvc0_context *nvc0)
if (tic->id < 0) {
tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
- PUSH_SPACE(push, 16);
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, txc->offset + (tic->id * 32));
- PUSH_DATA (push, txc->offset + (tic->id * 32));
- BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
- PUSH_DATA (push, 32);
- PUSH_DATA (push, 1);
- BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
- PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
- PUSH_DATAp(push, &tic->tic[0], 8);
+ nve4_p2mf_push_linear(&nvc0->base, nvc0->screen->txc, tic->id * 32,
+ NV_VRAM_DOMAIN(&nvc0->screen->base),
+ 32, tic->tic);
commands[0][n[0]++] = (tic->id << 4) | 1;
} else
--
2.10.1
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