[Mesa-dev] [PATCH 2/3] nvc0: add nvc0_screen_{tic,tsc}_lock()

Samuel Pitoiset samuel.pitoiset at gmail.com
Wed Oct 26 20:00:10 UTC 2016


Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.h  | 14 ++++++++++++++
 src/gallium/drivers/nouveau/nvc0/nvc0_tex.c     | 10 +++++-----
 src/gallium/drivers/nouveau/nvc0/nve4_compute.c |  4 ++--
 3 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index aff0308..86168f5 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -189,6 +189,20 @@ extern const struct nvc0_format nvc0_format_table[];
 extern const struct nvc0_vertex_format nvc0_vertex_format[];
 
 static inline void
+nvc0_screen_tic_lock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
+{
+   if (tic->id >= 0)
+      screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
+}
+
+static inline void
+nvc0_screen_tsc_lock(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)
+{
+   if (tsc->id >= 0)
+      screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
+}
+
+static inline void
 nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
 {
    if (tic->id >= 0)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index e57391e..23c9daa 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -506,7 +506,7 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
          PUSH_DATA (push, (tic->id << 4) | 1);
          NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_cache_flush_count, 1);
       }
-      nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
+      nvc0_screen_tic_lock(nvc0->screen, tic);
 
       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
       res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
@@ -568,7 +568,7 @@ nve4_validate_tic(struct nvc0_context *nvc0, unsigned s)
          BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
          PUSH_DATA (push, (tic->id << 4) | 1);
       }
-      nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
+      nvc0_screen_tic_lock(nvc0->screen, tic);
 
       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
       res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
@@ -639,7 +639,7 @@ nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
                                32, tsc->tsc);
          need_flush = true;
       }
-      nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
+      nvc0_screen_tsc_lock(nvc0->screen, tsc);
 
       commands[n++] = (tsc->id << 12) | (i << 4) | 1;
    }
@@ -682,7 +682,7 @@ nve4_validate_tsc(struct nvc0_context *nvc0, int s)
                                32, tsc->tsc);
          need_flush = true;
       }
-      nvc0->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
+      nvc0_screen_tsc_lock(nvc0->screen, tsc);
 
       nvc0->tex_handles[s][i] &= ~NVE4_TSC_ENTRY_INVALID;
       nvc0->tex_handles[s][i] |= tsc->id << 20;
@@ -1123,7 +1123,7 @@ gm107_validate_surfaces(struct nvc0_context *nvc0,
       BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
       PUSH_DATA (push, (tic->id << 4) | 1);
    }
-   nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
+   nvc0_screen_tic_lock(nvc0->screen, tic);
 
    res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
    res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
index 2c6de86..26732a1 100644
--- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
@@ -215,7 +215,7 @@ gm107_compute_validate_surfaces(struct nvc0_context *nvc0,
       BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), 1);
       PUSH_DATA (push, (tic->id << 4) | 1);
    }
-   nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
+   nvc0_screen_tic_lock(nvc0->screen, tic);
 
    res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
    res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
@@ -696,7 +696,7 @@ nve4_compute_validate_textures(struct nvc0_context *nvc0)
       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
          commands[1][n[1]++] = (tic->id << 4) | 1;
       }
-      nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
+      nvc0_screen_tic_lock(nvc0->screen, tic);
 
       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
       res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
-- 
2.10.1



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