[Mesa-dev] [RFC 01/11] i965: Pull shader_info out of gl_program rather than nir_shader
Jason Ekstrand
jason at jlekstrand.net
Fri Oct 28 20:46:30 UTC 2016
This commit modifies all of the state upload and codegen code to pull the
shader_info out of gl_program rather than nir_shader. In the GL driver,
the pointer in nir_shader just points to gl_program::shader_info anyway so
there's no real point in pulling it from the nir_shader.
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_tcs.c | 15 ++++++++-------
src/mesa/drivers/dri/i965/brw_tes.c | 8 ++++----
src/mesa/drivers/dri/i965/brw_vs.c | 4 ++--
src/mesa/drivers/dri/i965/brw_wm.c | 6 +++---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 ++++++------
6 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index cd893b1..9f5db45 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -1212,7 +1212,7 @@ brw_assign_common_binding_table_offsets(gl_shader_stage stage,
stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
}
- if (prog->nir->info->uses_texture_gather) {
+ if (prog->info.uses_texture_gather) {
if (devinfo->gen >= 8) {
stage_prog_data->binding_table.gather_texture_start =
stage_prog_data->binding_table.texture_start;
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index 58d080d..558de2d 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -37,6 +37,7 @@
static nir_shader *
create_passthrough_tcs(const struct brw_compiler *compiler,
+ shader_info *info,
const nir_shader_compiler_options *options,
const struct brw_tcs_prog_key *key)
{
@@ -50,10 +51,10 @@ create_passthrough_tcs(const struct brw_compiler *compiler,
nir_ssa_def *invoc_id =
nir_load_system_value(&b, nir_intrinsic_load_invocation_id, 0);
- nir->info->inputs_read = key->outputs_written;
- nir->info->outputs_written = key->outputs_written;
- nir->info->tcs.vertices_out = key->input_vertices;
- nir->info->name = ralloc_strdup(nir, "passthrough");
+ info->inputs_read = key->outputs_written;
+ info->outputs_written = key->outputs_written;
+ info->tcs.vertices_out = key->input_vertices;
+ info->name = ralloc_strdup(nir, "passthrough");
nir->num_uniforms = 8 * sizeof(uint32_t);
var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_0");
@@ -186,7 +187,7 @@ brw_codegen_tcs_prog(struct brw_context *brw,
*/
const nir_shader_compiler_options *options =
ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions;
- nir = create_passthrough_tcs(compiler, options, key);
+ nir = create_passthrough_tcs(compiler, &tcp->program.info, options, key);
}
memset(&prog_data, 0, sizeof(prog_data));
@@ -421,8 +422,8 @@ brw_tcs_precompile(struct gl_context *ctx,
key.tes_primitive_mode = GL_TRIANGLES;
}
- key.outputs_written = prog->nir->info->outputs_written;
- key.patch_outputs_written = prog->nir->info->patch_outputs_written;
+ key.outputs_written = prog->info.outputs_written;
+ key.patch_outputs_written = prog->info.patch_outputs_written;
success = brw_codegen_tcs_prog(brw, shader_prog, btcp, &key);
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index 6060c76..b8c26df 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -310,14 +310,14 @@ brw_tes_precompile(struct gl_context *ctx,
memset(&key, 0, sizeof(key));
key.program_string_id = btep->id;
- key.inputs_read = prog->nir->info->inputs_read;
- key.patch_inputs_read = prog->nir->info->patch_inputs_read;
+ key.inputs_read = prog->info.inputs_read;
+ key.patch_inputs_read = prog->info.patch_inputs_read;
if (shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]) {
struct gl_program *tcp =
shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]->Program;
- key.inputs_read |= tcp->nir->info->outputs_written;
- key.patch_inputs_read |= tcp->nir->info->patch_outputs_written;
+ key.inputs_read |= tcp->info.outputs_written;
+ key.patch_inputs_read |= tcp->info.patch_outputs_written;
}
/* Ignore gl_TessLevelInner/Outer - they're system values. */
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 842c516..b5111d8 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -335,7 +335,7 @@ brw_vs_populate_key(struct brw_context *brw,
}
}
- if (prog->nir->info->outputs_written &
+ if (prog->info.outputs_written &
(VARYING_BIT_COL0 | VARYING_BIT_COL1 | VARYING_BIT_BFC0 |
VARYING_BIT_BFC1)) {
/* _NEW_LIGHT | _NEW_BUFFERS */
@@ -394,7 +394,7 @@ brw_vs_precompile(struct gl_context *ctx,
brw_setup_tex_for_precompile(brw, &key.tex, prog);
key.program_string_id = bvp->id;
key.clamp_vertex_color =
- (prog->nir->info->outputs_written &
+ (prog->info.outputs_written &
(VARYING_BIT_COL0 | VARYING_BIT_COL1 | VARYING_BIT_BFC0 |
VARYING_BIT_BFC1));
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index f433ed6..31ffde5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -61,7 +61,7 @@ assign_fs_binding_table_offsets(const struct gen_device_info *devinfo,
shader_prog, prog, &prog_data->base,
next_binding_table_offset);
- if (prog->nir->info->outputs_read && !key->coherent_fb_fetch) {
+ if (prog->info.outputs_read && !key->coherent_fb_fetch) {
prog_data->binding_table.render_target_read_start =
next_binding_table_offset;
next_binding_table_offset += key->nr_color_regions;
@@ -359,7 +359,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
* a shader w/a on IVB; fixable with just SCS on HSW.
*/
if (brw->gen == 7 && !brw->is_haswell &&
- prog->nir->info->uses_texture_gather) {
+ prog->info.uses_texture_gather) {
if (img->InternalFormat == GL_RG32F)
key->gather_channel_quirk_mask |= 1 << s;
}
@@ -367,7 +367,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
/* Gen6's gather4 is broken for UINT/SINT; we treat them as
* UNORM/FLOAT instead and fix it in the shader.
*/
- if (brw->gen == 6 && prog->nir->info->uses_texture_gather) {
+ if (brw->gen == 6 && prog->info.uses_texture_gather) {
key->gen6_gather_wa[s] = gen6_gather_workaround(img->InternalFormat);
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index fcd753c..fa1fb0c 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1290,15 +1290,15 @@ brw_update_texture_surfaces(struct brw_context *brw)
* allows the surface format to be overriden for only the
* gather4 messages. */
if (brw->gen < 8) {
- if (vs && vs->nir->info->uses_texture_gather)
+ if (vs && vs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, vs, &brw->vs.base, true, 0);
- if (tcs && tcs->nir->info->uses_texture_gather)
+ if (tcs && tcs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, tcs, &brw->tcs.base, true, 0);
- if (tes && tes->nir->info->uses_texture_gather)
+ if (tes && tes->info.uses_texture_gather)
update_stage_texture_surfaces(brw, tes, &brw->tes.base, true, 0);
- if (gs && gs->nir->info->uses_texture_gather)
+ if (gs && gs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, gs, &brw->gs.base, true, 0);
- if (fs && fs->nir->info->uses_texture_gather)
+ if (fs && fs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, fs, &brw->wm.base, true, 0);
}
@@ -1343,7 +1343,7 @@ brw_update_cs_texture_surfaces(struct brw_context *brw)
* gather4 messages.
*/
if (brw->gen < 8) {
- if (cs && cs->nir->info->uses_texture_gather)
+ if (cs && cs->info.uses_texture_gather)
update_stage_texture_surfaces(brw, cs, &brw->cs.base, true, 0);
}
--
2.5.0.400.gff86faf
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