[Mesa-dev] [PATCH 5/5] radeonsi: flush TC L2 before using a compute indirect buffer

[Nicolai Hähnle]

This series is

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

On 09.09.2016 17:05, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> There is no known test for this.
>
> Cc: 12.0 <mesa-stable at lists.freedesktop.org>
> ---
>  src/gallium/drivers/radeonsi/si_compute.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
> index f43c616..d988214 100644
> --- a/src/gallium/drivers/radeonsi/si_compute.c
> +++ b/src/gallium/drivers/radeonsi/si_compute.c
> @@ -457,24 +457,32 @@ static void si_launch_grid(
>  		info->block[0] * info->block[1] * info->block[2] > 256;
>
>  	if (cs_regalloc_hang)
>  		sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
>  				 SI_CONTEXT_CS_PARTIAL_FLUSH;
>
>  	si_decompress_compute_textures(sctx);
>
>  	/* Add buffer sizes for memory checking in need_cs_space. */
>  	r600_context_add_resource_size(ctx, &program->shader.bo->b.b);
> -	if (info->indirect)
> -		r600_context_add_resource_size(ctx, info->indirect);
>  	/* TODO: add the scratch buffer */
>
> +	if (info->indirect) {
> +		r600_context_add_resource_size(ctx, info->indirect);
> +
> +		/* The hw doesn't read the indirect buffer via TC L2. */
> +		if (r600_resource(info->indirect)->TC_L2_dirty) {
> +			sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
> +			r600_resource(info->indirect)->TC_L2_dirty = false;
> +		}
> +	}
> +
>  	si_need_cs_space(sctx);
>
>  	if (!sctx->cs_shader_state.initialized)
>  		si_initialize_compute(sctx);
>
>  	if (sctx->b.flags)
>  		si_emit_cache_flush(sctx);
>
>  	if (!si_switch_compute_shader(sctx, program, &program->shader, info->pc))
>  		return;
>