[Mesa-dev] [PATCH 1/4] intel/isl: Allow valign2 for texture-only Y-tiled surfaces on gen7

[Chad Versace]

On Fri 09 Sep 2016, Jason Ekstrand wrote:
> The restriction that Y-tiled surfaces must have valign == 4 only aplies to
> render targets but we were applying it universally.  This causes problems
> if R32G32B32_SFLOAT is used because it requires valign == 2; this should be
     ^^^^^^^^^^^^^^^^
That isl format doesn't exist. Did you mean R32B32B32_FLOAT (sans S)?

> okay because you can't render to that format.
> 
> Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
> Cc: Chad Versace <chad at kiwitree.net>
> ---
>  src/intel/isl/isl_gen7.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
> index 02273f8..f3d8428 100644
> --- a/src/intel/isl/isl_gen7.c
> +++ b/src/intel/isl/isl_gen7.c
> @@ -354,7 +354,8 @@ gen7_choose_valign_el(const struct isl_device *dev,
>      */
>     if (isl_surf_usage_is_depth(info->usage) ||
>         info->samples > 1 ||
> -       tiling == ISL_TILING_Y0) {
> +       ((info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
> +        tiling == ISL_TILING_Y0)) {
>        require_valign4 = true;
>     }

Did the buggy code trigger the assertion on line 390?
    assert(!require_valign2 || !require_valign4);    
If not, then something is suspicious.

Fix the commit message and this is
Reviewed-by: Chad Versace <chadversary at chromium.org>