[Mesa-dev] [PATCH 2/4] i916/blorp: Align vertex buffers to 64B

[Jason Ekstrand]

Two people have independently pointed out the i916 typo.  I've fixed it
locally.

On Fri, Mar 31, 2017 at 4:17 PM, Jason Ekstrand <jason at jlekstrand.net>
wrote:

> Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>
> ---
>  src/mesa/drivers/dri/i965/genX_blorp_exec.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> index f9334ee..b6122a3 100644
> --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> @@ -122,8 +122,19 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch,
> uint32_t size,
>     assert(batch->blorp->driver_ctx == batch->driver_batch);
>     struct brw_context *brw = batch->driver_batch;
>
> +   /* From the Sky Lake PRM, 3DSTATE_VERTEX_BUFFERS:
> +    *
> +    *    "The VF cache needs to be invalidated before binding and then
> using
> +    *    Vertex Buffers that overlap with any previously bound Vertex
> Buffer
> +    *    (at a 64B granularity) since the last invalidation.  A VF cache
> +    *    invalidate is performed by setting the "VF Cache Invalidation
> Enable"
> +    *    bit in PIPE_CONTROL."
> +    *
> +    * In order to avoid this problem, we align all vertex buffer
> allocations
> +    * to 64 bytes.
> +    */
>     uint32_t offset;
> -   void *data = brw_state_batch(brw, size, 32, &offset);
> +   void *data = brw_state_batch(brw, size, 64, &offset);
>
>     *addr = (struct blorp_address) {
>        .buffer = brw->batch.bo,
> --
> 2.5.0.400.gff86faf
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/mesa-dev/attachments/20170401/e004ce55/attachment.html>